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ShiftRegInit: use the rocket-chip version since it is there now
[sifive-blocks.git]
/
src
/
main
/
scala
/
devices
/
uart
/
drwxr-xr-x
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-rw-r--r--
7449
UART.scala
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-rw-r--r--
277
UARTCtrlRegs.scala
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-rw-r--r--
1821
UARTPeriphery.scala
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