XilinxVC707MIG : place upper 2GB of 4GB depth configuration in upper address range

[sifive-blocks.git] / src / main / scala / devices / xilinxvc707mig / XilinxVC707MIG.scala

diff --git a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
index f6ae153107a4ff9558056f54c3703004baab7643..48dedbc41e8f5ebbb4102292efb2a579681db317 100644 (file)
--- a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
+++ b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
@@ -3,27 +3,35 @@ package sifive.blocks.devices.xilinxvc707mig
 
 import Chisel._
 import chisel3.experimental.{Analog,attach}
-import config._
-import diplomacy._
-import uncore.tilelink2._
-import uncore.axi4._
-import rocketchip._
+import freechips.rocketchip.amba.axi4._
+import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.coreplex._
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.tilelink._
 import sifive.blocks.ip.xilinx.vc707mig.{VC707MIGIOClocksReset, VC707MIGIODDR, vc707mig}
 
-trait HasXilinxVC707MIGParameters {
-}
+case class XilinxVC707MIGParams(
+  address : Seq[AddressSet],
+  depthGB : Int
+)
 
-class XilinxVC707MIGPads extends Bundle with VC707MIGIODDR
+class XilinxVC707MIGPads(depthGB : Integer) extends VC707MIGIODDR(depthGB)
 
-class XilinxVC707MIGIO extends Bundle with VC707MIGIODDR
-                                      with VC707MIGIOClocksReset
+class XilinxVC707MIGIO(depthGB : Integer) extends VC707MIGIODDR(depthGB) with VC707MIGIOClocksReset
 
-class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC707MIGParameters {
+class XilinxVC707MIG(c : XilinxVC707MIGParams)(implicit p: Parameters) extends LazyModule {
+  // Supported depth configurations
+  require((c.depthGB==1) || (c.depthGB==4),"XilinxVC707MIG supports 1GB and 4GB depth configuraton only")
+  // Suppoted address map configuratons
+  if(c.depthGB==1) require(c.address == Seq(AddressSet(0x80000000L ,  0x80000000L-1)))   //2GB   @ 2GB
+  if(c.depthGB==4) require(c.address == Seq(AddressSet(0x80000000L,   0x80000000L-1),    //2GB   @ 2GB
+                                            AddressSet(0x2080000000L, 0x80000000L-1)))   //2GB   @ 130GB
+  
   val device = new MemoryDevice
   val node = TLInputNode()
   val axi4 = AXI4InternalOutputNode(Seq(AXI4SlavePortParameters(
-    slaves = Seq(AXI4SlaveParameters(
-      address = Seq(AddressSet(p(ExtMem).base, p(ExtMem).size-1)),
+      slaves = Seq(AXI4SlaveParameters(
+      address       = c.address,
       resources     = device.reg,
       regionType    = RegionType.UNCACHED,
       executable    = true,
@@ -32,9 +40,9 @@ class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC
     beatBytes = 8)))
 
   val xing    = LazyModule(new TLAsyncCrossing)
-  val toaxi4  = LazyModule(new TLToAXI4(beatBytes = 8))
+  val toaxi4  = LazyModule(new TLToAXI4(beatBytes = 8, adapterName = Some("mem"), stripBits = 1))
   val indexer = LazyModule(new AXI4IdIndexer(idBits = 4))
-  val deint   = LazyModule(new AXI4Deinterleaver(p(coreplex.CacheBlockBytes)))
+  val deint   = LazyModule(new AXI4Deinterleaver(p(CacheBlockBytes)))
   val yank    = LazyModule(new AXI4UserYanker)
   val buffer  = LazyModule(new AXI4Buffer)
 
@@ -48,12 +56,12 @@ class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC
 
   lazy val module = new LazyModuleImp(this) {
     val io = new Bundle {
-      val port = new XilinxVC707MIGIO
+      val port = new XilinxVC707MIGIO(c.depthGB)
       val tl = node.bundleIn
     }
 
     //MIG black box instantiation
-    val blackbox = Module(new vc707mig)
+    val blackbox = Module(new vc707mig(c.depthGB))
 
     //pins to top level
 
@@ -102,9 +110,21 @@ class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC
     //app_ref_ack             := unconnected
     //app_zq_ack              := unconnected
 
+    //if(bits(37)==1) {  (upper address range)
+    // axiaddress = least sig 37 bits of address
+    //else{ (low address range)
+    // axiaddress = address ^ 0x8000000
+    //}
+
+    val awaddr = axi_async.aw.bits.addr;
+    val awbit31 = awaddr(37) & awaddr(31)
+
+    val araddr = axi_async.ar.bits.addr;
+    val arbit31 = araddr(37) & araddr(31)
+
     //slave AXI interface write address ports
     blackbox.io.s_axi_awid    := axi_async.aw.bits.id
-    blackbox.io.s_axi_awaddr  := axi_async.aw.bits.addr //truncation ??
+    blackbox.io.s_axi_awaddr  := awaddr //truncated
     blackbox.io.s_axi_awlen   := axi_async.aw.bits.len
     blackbox.io.s_axi_awsize  := axi_async.aw.bits.size
     blackbox.io.s_axi_awburst := axi_async.aw.bits.burst
@@ -130,7 +150,7 @@ class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC
 
     //slave AXI interface read address ports
     blackbox.io.s_axi_arid    := axi_async.ar.bits.id
-    blackbox.io.s_axi_araddr  := axi_async.ar.bits.addr //truncation ??
+    blackbox.io.s_axi_araddr  := araddr // truncated
     blackbox.io.s_axi_arlen   := axi_async.ar.bits.len
     blackbox.io.s_axi_arsize  := axi_async.ar.bits.size
     blackbox.io.s_axi_arburst := axi_async.ar.bits.burst