XilinxVC707MIG : place upper 2GB of 4GB depth configuration in upper address range
authorHenry Styles <hes@sifive.com>
Tue, 8 Aug 2017 17:53:22 +0000 (10:53 -0700)
committerHenry Styles <hes@sifive.com>
Mon, 14 Aug 2017 21:57:11 +0000 (14:57 -0700)
commit6a5fba5ebec53e3fbab41dc39ad1db1e02e94322
tree293d2c03cd19398f3e2b0cd2d41285480c535655
parent360fe7e2a9c8f9982d1822baf6e56002a3705f9a
XilinxVC707MIG : place upper 2GB of 4GB depth configuration in upper address range
src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala