src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.devices.xilinxvc707mig
   3
   4 import Chisel._
   5 import chisel3.experimental.{Analog,attach}
   6 import freechips.rocketchip.amba.axi4._
   7 import freechips.rocketchip.config.Parameters
   8 import freechips.rocketchip.coreplex._
   9 import freechips.rocketchip.diplomacy._
  10 import freechips.rocketchip.tilelink._
  11 import sifive.blocks.ip.xilinx.vc707mig.{VC707MIGIOClocksReset, VC707MIGIODDR, vc707mig}
  12
  13 case class XilinxVC707MIGParams(
  14   address : Seq[AddressSet],
  15   depthGB : Int
  16 )
  17
  18 class XilinxVC707MIGPads(depthGB : Integer) extends VC707MIGIODDR(depthGB)
  19
  20 class XilinxVC707MIGIO(depthGB : Integer) extends VC707MIGIODDR(depthGB) with VC707MIGIOClocksReset
  21
  22 class XilinxVC707MIG(c : XilinxVC707MIGParams)(implicit p: Parameters) extends LazyModule {
  23   // Supported depth configurations
  24   require((c.depthGB==1) || (c.depthGB==4),"XilinxVC707MIG supports 1GB and 4GB depth configuraton only")
  25   // Suppoted address map configuratons
  26   if(c.depthGB==1) require(c.address == Seq(AddressSet(0x80000000L ,  0x80000000L-1)))   //2GB   @ 2GB
  27   if(c.depthGB==4) require(c.address == Seq(AddressSet(0x80000000L,   0x80000000L-1),    //2GB   @ 2GB
  28                                             AddressSet(0x2080000000L, 0x80000000L-1)))   //2GB   @ 130GB
  29
  30   val device = new MemoryDevice
  31   val node = TLInputNode()
  32   val axi4 = AXI4InternalOutputNode(Seq(AXI4SlavePortParameters(
  33       slaves = Seq(AXI4SlaveParameters(
  34       address       = c.address,
  35       resources     = device.reg,
  36       regionType    = RegionType.UNCACHED,
  37       executable    = true,
  38       supportsWrite = TransferSizes(1, 256*8),
  39       supportsRead  = TransferSizes(1, 256*8))),
  40     beatBytes = 8)))
  41
  42   val xing    = LazyModule(new TLAsyncCrossing)
  43   val toaxi4  = LazyModule(new TLToAXI4(beatBytes = 8, adapterName = Some("mem"), stripBits = 1))
  44   val indexer = LazyModule(new AXI4IdIndexer(idBits = 4))
  45   val deint   = LazyModule(new AXI4Deinterleaver(p(CacheBlockBytes)))
  46   val yank    = LazyModule(new AXI4UserYanker)
  47   val buffer  = LazyModule(new AXI4Buffer)
  48
  49   xing.node := node
  50   val monitor = (toaxi4.node := xing.node)
  51   axi4 := buffer.node
  52   buffer.node := yank.node
  53   yank.node := deint.node
  54   deint.node := indexer.node
  55   indexer.node := toaxi4.node
  56
  57   lazy val module = new LazyModuleImp(this) {
  58     val io = new Bundle {
  59       val port = new XilinxVC707MIGIO(c.depthGB)
  60       val tl = node.bundleIn
  61     }
  62
  63     //MIG black box instantiation
  64     val blackbox = Module(new vc707mig(c.depthGB))
  65
  66     //pins to top level
  67
  68     //inouts
  69     attach(io.port.ddr3_dq,blackbox.io.ddr3_dq)
  70     attach(io.port.ddr3_dqs_n,blackbox.io.ddr3_dqs_n)
  71     attach(io.port.ddr3_dqs_p,blackbox.io.ddr3_dqs_p)
  72
  73     //outputs
  74     io.port.ddr3_addr         := blackbox.io.ddr3_addr
  75     io.port.ddr3_ba           := blackbox.io.ddr3_ba
  76     io.port.ddr3_ras_n        := blackbox.io.ddr3_ras_n
  77     io.port.ddr3_cas_n        := blackbox.io.ddr3_cas_n
  78     io.port.ddr3_we_n         := blackbox.io.ddr3_we_n
  79     io.port.ddr3_reset_n      := blackbox.io.ddr3_reset_n
  80     io.port.ddr3_ck_p         := blackbox.io.ddr3_ck_p
  81     io.port.ddr3_ck_n         := blackbox.io.ddr3_ck_n
  82     io.port.ddr3_cke          := blackbox.io.ddr3_cke
  83     io.port.ddr3_cs_n         := blackbox.io.ddr3_cs_n
  84     io.port.ddr3_dm           := blackbox.io.ddr3_dm
  85     io.port.ddr3_odt          := blackbox.io.ddr3_odt
  86
  87     //inputs
  88     //NO_BUFFER clock
  89     blackbox.io.sys_clk_i     := io.port.sys_clk_i
  90
  91     //user interface signals
  92     val axi_async = axi4.bundleIn(0)
  93     xing.module.io.in_clock := clock
  94     xing.module.io.in_reset := reset
  95     xing.module.io.out_clock := blackbox.io.ui_clk
  96     xing.module.io.out_reset := blackbox.io.ui_clk_sync_rst
  97     (Seq(toaxi4, indexer, deint, yank, buffer) ++ monitor) foreach { lm =>
  98       lm.module.clock := blackbox.io.ui_clk
  99       lm.module.reset := blackbox.io.ui_clk_sync_rst
 100     }
 101
 102     io.port.ui_clk            := blackbox.io.ui_clk
 103     io.port.ui_clk_sync_rst   := blackbox.io.ui_clk_sync_rst
 104     io.port.mmcm_locked       := blackbox.io.mmcm_locked
 105     blackbox.io.aresetn       := io.port.aresetn
 106     blackbox.io.app_sr_req    := Bool(false)
 107     blackbox.io.app_ref_req   := Bool(false)
 108     blackbox.io.app_zq_req    := Bool(false)
 109     //app_sr_active           := unconnected
 110     //app_ref_ack             := unconnected
 111     //app_zq_ack              := unconnected
 112
 113     //if(bits(37)==1) {  (upper address range)
 114     // axiaddress = least sig 37 bits of address
 115     //else{ (low address range)
 116     // axiaddress = address ^ 0x8000000
 117     //}
 118
 119     val awaddr = axi_async.aw.bits.addr;
 120     val awbit31 = awaddr(37) & awaddr(31)
 121
 122     val araddr = axi_async.ar.bits.addr;
 123     val arbit31 = araddr(37) & araddr(31)
 124
 125     //slave AXI interface write address ports
 126     blackbox.io.s_axi_awid    := axi_async.aw.bits.id
 127     blackbox.io.s_axi_awaddr  := awaddr //truncated
 128     blackbox.io.s_axi_awlen   := axi_async.aw.bits.len
 129     blackbox.io.s_axi_awsize  := axi_async.aw.bits.size
 130     blackbox.io.s_axi_awburst := axi_async.aw.bits.burst
 131     blackbox.io.s_axi_awlock  := axi_async.aw.bits.lock
 132     blackbox.io.s_axi_awcache := UInt("b0011")
 133     blackbox.io.s_axi_awprot  := axi_async.aw.bits.prot
 134     blackbox.io.s_axi_awqos   := axi_async.aw.bits.qos
 135     blackbox.io.s_axi_awvalid := axi_async.aw.valid
 136     axi_async.aw.ready        := blackbox.io.s_axi_awready
 137
 138     //slave interface write data ports
 139     blackbox.io.s_axi_wdata   := axi_async.w.bits.data
 140     blackbox.io.s_axi_wstrb   := axi_async.w.bits.strb
 141     blackbox.io.s_axi_wlast   := axi_async.w.bits.last
 142     blackbox.io.s_axi_wvalid  := axi_async.w.valid
 143     axi_async.w.ready         := blackbox.io.s_axi_wready
 144
 145     //slave interface write response
 146     blackbox.io.s_axi_bready  := axi_async.b.ready
 147     axi_async.b.bits.id       := blackbox.io.s_axi_bid
 148     axi_async.b.bits.resp     := blackbox.io.s_axi_bresp
 149     axi_async.b.valid         := blackbox.io.s_axi_bvalid
 150
 151     //slave AXI interface read address ports
 152     blackbox.io.s_axi_arid    := axi_async.ar.bits.id
 153     blackbox.io.s_axi_araddr  := araddr // truncated
 154     blackbox.io.s_axi_arlen   := axi_async.ar.bits.len
 155     blackbox.io.s_axi_arsize  := axi_async.ar.bits.size
 156     blackbox.io.s_axi_arburst := axi_async.ar.bits.burst
 157     blackbox.io.s_axi_arlock  := axi_async.ar.bits.lock
 158     blackbox.io.s_axi_arcache := UInt("b0011")
 159     blackbox.io.s_axi_arprot  := axi_async.ar.bits.prot
 160     blackbox.io.s_axi_arqos   := axi_async.ar.bits.qos
 161     blackbox.io.s_axi_arvalid := axi_async.ar.valid
 162     axi_async.ar.ready        := blackbox.io.s_axi_arready
 163
 164     //slace AXI interface read data ports
 165     blackbox.io.s_axi_rready  := axi_async.r.ready
 166     axi_async.r.bits.id       := blackbox.io.s_axi_rid
 167     axi_async.r.bits.data     := blackbox.io.s_axi_rdata
 168     axi_async.r.bits.resp     := blackbox.io.s_axi_rresp
 169     axi_async.r.bits.last     := blackbox.io.s_axi_rlast
 170     axi_async.r.valid         := blackbox.io.s_axi_rvalid
 171
 172     //misc
 173     io.port.init_calib_complete := blackbox.io.init_calib_complete
 174     blackbox.io.sys_rst       :=io.port.sys_rst
 175     //mig.device_temp         :- unconnceted
 176   }
 177 }