package sifive.blocks.devices.xilinxvc707mig
import Chisel._
-import config._
-import diplomacy._
-import uncore.tilelink2._
-import uncore.axi4._
-import rocketchip._
-import sifive.blocks.ip.xilinx.vc707mig.{VC707MIGUnidirectionalIOClocksReset, VC707MIGUnidirectionalIODDR, vc707mig}
-
-trait HasXilinxVC707MIGParameters {
-}
-
-class XilinxVC707MIGPads extends Bundle with VC707MIGUnidirectionalIODDR {
- val _inout_ddr3_dq = Bits(OUTPUT,64)
- val _inout_ddr3_dqs_n = Bits(OUTPUT,8)
- val _inout_ddr3_dqs_p = Bits(OUTPUT,8)
-}
-
-class XilinxVC707MIGIO extends Bundle with VC707MIGUnidirectionalIODDR
- with VC707MIGUnidirectionalIOClocksReset {
- val _inout_ddr3_dq = Bits(OUTPUT,64)
- val _inout_ddr3_dqs_n = Bits(OUTPUT,8)
- val _inout_ddr3_dqs_p = Bits(OUTPUT,8)
-}
-
-class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC707MIGParameters {
+import chisel3.experimental.{Analog,attach}
+import freechips.rocketchip.amba.axi4._
+import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.coreplex._
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.tilelink._
+import sifive.blocks.ip.xilinx.vc707mig.{VC707MIGIOClocksReset, VC707MIGIODDR, vc707mig}
+
+case class XilinxVC707MIGParams(
+ address : Seq[AddressSet],
+ depthGB : Int
+)
+
+class XilinxVC707MIGPads(depthGB : Integer) extends VC707MIGIODDR(depthGB)
+
+class XilinxVC707MIGIO(depthGB : Integer) extends VC707MIGIODDR(depthGB) with VC707MIGIOClocksReset
+
+class XilinxVC707MIG(c : XilinxVC707MIGParams)(implicit p: Parameters) extends LazyModule {
+ // Supported depth configurations
+ require((c.depthGB==1) || (c.depthGB==4),"XilinxVC707MIG supports 1GB and 4GB depth configuraton only")
+ // Suppoted address map configuratons
+ if(c.depthGB==1) require(c.address == Seq(AddressSet(0x80000000L , 0x80000000L-1))) //2GB @ 2GB
+ if(c.depthGB==4) require(c.address == Seq(AddressSet(0x80000000L, 0x80000000L-1), //2GB @ 2GB
+ AddressSet(0x2080000000L, 0x80000000L-1))) //2GB @ 130GB
+
+ val device = new MemoryDevice
val node = TLInputNode()
val axi4 = AXI4InternalOutputNode(Seq(AXI4SlavePortParameters(
- slaves = Seq(AXI4SlaveParameters(
- address = Seq(AddressSet(p(ExtMem).base, p(ExtMem).size-1)),
+ slaves = Seq(AXI4SlaveParameters(
+ address = c.address,
+ resources = device.reg,
regionType = RegionType.UNCACHED,
executable = true,
supportsWrite = TransferSizes(1, 256*8),
- supportsRead = TransferSizes(1, 256*8),
- interleavedId = Some(0))),
+ supportsRead = TransferSizes(1, 256*8))),
beatBytes = 8)))
- val xing = LazyModule(new TLAsyncCrossing)
- val toaxi4 = LazyModule(new TLToAXI4(idBits = 4))
+ val xing = LazyModule(new TLAsyncCrossing)
+ val toaxi4 = LazyModule(new TLToAXI4(beatBytes = 8, adapterName = Some("mem"), stripBits = 1))
+ val indexer = LazyModule(new AXI4IdIndexer(idBits = 4))
+ val deint = LazyModule(new AXI4Deinterleaver(p(CacheBlockBytes)))
+ val yank = LazyModule(new AXI4UserYanker)
+ val buffer = LazyModule(new AXI4Buffer)
xing.node := node
val monitor = (toaxi4.node := xing.node)
- axi4 := toaxi4.node
+ axi4 := buffer.node
+ buffer.node := yank.node
+ yank.node := deint.node
+ deint.node := indexer.node
+ indexer.node := toaxi4.node
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {
- val port = new XilinxVC707MIGIO
+ val port = new XilinxVC707MIGIO(c.depthGB)
val tl = node.bundleIn
}
//MIG black box instantiation
- val blackbox = Module(new vc707mig)
+ val blackbox = Module(new vc707mig(c.depthGB))
//pins to top level
//inouts
- io.port._inout_ddr3_dq := blackbox.io.ddr3_dq
- io.port._inout_ddr3_dqs_n := blackbox.io.ddr3_dqs_n
- io.port._inout_ddr3_dqs_p := blackbox.io.ddr3_dqs_p
+ attach(io.port.ddr3_dq,blackbox.io.ddr3_dq)
+ attach(io.port.ddr3_dqs_n,blackbox.io.ddr3_dqs_n)
+ attach(io.port.ddr3_dqs_p,blackbox.io.ddr3_dqs_p)
//outputs
io.port.ddr3_addr := blackbox.io.ddr3_addr
io.port.ddr3_odt := blackbox.io.ddr3_odt
//inputs
- //differential system clock
- blackbox.io.sys_clk_n := io.port.sys_clk_n
- blackbox.io.sys_clk_p := io.port.sys_clk_p
+ //NO_BUFFER clock
+ blackbox.io.sys_clk_i := io.port.sys_clk_i
//user interface signals
val axi_async = axi4.bundleIn(0)
xing.module.io.in_reset := reset
xing.module.io.out_clock := blackbox.io.ui_clk
xing.module.io.out_reset := blackbox.io.ui_clk_sync_rst
- toaxi4.module.clock := blackbox.io.ui_clk
- toaxi4.module.reset := blackbox.io.ui_clk_sync_rst
- monitor.foreach { lm =>
+ (Seq(toaxi4, indexer, deint, yank, buffer) ++ monitor) foreach { lm =>
lm.module.clock := blackbox.io.ui_clk
lm.module.reset := blackbox.io.ui_clk_sync_rst
}
//app_ref_ack := unconnected
//app_zq_ack := unconnected
+ //if(bits(37)==1) { (upper address range)
+ // axiaddress = least sig 37 bits of address
+ //else{ (low address range)
+ // axiaddress = address ^ 0x8000000
+ //}
+
+ val awaddr = axi_async.aw.bits.addr;
+ val awbit31 = awaddr(37) & awaddr(31)
+
+ val araddr = axi_async.ar.bits.addr;
+ val arbit31 = araddr(37) & araddr(31)
+
//slave AXI interface write address ports
blackbox.io.s_axi_awid := axi_async.aw.bits.id
- blackbox.io.s_axi_awaddr := axi_async.aw.bits.addr //truncation ??
+ blackbox.io.s_axi_awaddr := awaddr //truncated
blackbox.io.s_axi_awlen := axi_async.aw.bits.len
blackbox.io.s_axi_awsize := axi_async.aw.bits.size
blackbox.io.s_axi_awburst := axi_async.aw.bits.burst
//slave AXI interface read address ports
blackbox.io.s_axi_arid := axi_async.ar.bits.id
- blackbox.io.s_axi_araddr := axi_async.ar.bits.addr //truncation ??
+ blackbox.io.s_axi_araddr := araddr // truncated
blackbox.io.s_axi_arlen := axi_async.ar.bits.len
blackbox.io.s_axi_arsize := axi_async.ar.bits.size
blackbox.io.s_axi_arburst := axi_async.ar.bits.burst
projects / sifive-blocks.git / blobdiff