Refactor package hierarchy. (#25)

[sifive-blocks.git] / src / main / scala / devices / xilinxvc707mig / XilinxVC707MIGPeriphery.scala

diff --git a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala
index 4586949c0eada15181f58e5c4186f7118fa87841..540821ecc4b336e90ede107e73851cd088b2edce 100644 (file)
--- a/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala
+++ b/src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala
@@ -2,25 +2,28 @@
 package sifive.blocks.devices.xilinxvc707mig
 
 import Chisel._
-import diplomacy._
-import rocketchip.{TopNetwork,TopNetworkModule,TopNetworkBundle}
-import coreplex.BankedL2Config
+import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
+import freechips.rocketchip.chip.HasSystemNetworks
 
-trait PeripheryXilinxVC707MIG extends TopNetwork {
-  val module: PeripheryXilinxVC707MIGModule
+trait HasPeripheryXilinxVC707MIG extends HasSystemNetworks {
+  val module: HasPeripheryXilinxVC707MIGModuleImp
 
   val xilinxvc707mig = LazyModule(new XilinxVC707MIG)
-  require(p(BankedL2Config).nMemoryChannels == 1, "Coreplex must have 1 master memory port")
+  require(nMemoryChannels == 1, "Coreplex must have 1 master memory port")
   xilinxvc707mig.node := mem(0).node
 }
 
-trait PeripheryXilinxVC707MIGBundle extends TopNetworkBundle {
-  val xilinxvc707mig = new XilinxVC707MIGIO
+trait HasPeripheryXilinxVC707MIGBundle {
+  val xilinxvc707mig: XilinxVC707MIGIO
+  def connectXilinxVC707MIGToPads(pads: XilinxVC707MIGPads) {
+    pads <> xilinxvc707mig
+  }
 }
 
-trait PeripheryXilinxVC707MIGModule extends TopNetworkModule {
-  val outer: PeripheryXilinxVC707MIG
-  val io: PeripheryXilinxVC707MIGBundle
+trait HasPeripheryXilinxVC707MIGModuleImp extends LazyMultiIOModuleImp
+    with HasPeripheryXilinxVC707MIGBundle {
+  val outer: HasPeripheryXilinxVC707MIG
+  val xilinxvc707mig = IO(new XilinxVC707MIGIO)
 
-  io.xilinxvc707mig <> outer.xilinxvc707mig.module.io.port
+  xilinxvc707mig <> outer.xilinxvc707mig.module.io.port
 }