Refactor package hierarchy. (#25)

[sifive-blocks.git] / src / main / scala / devices / xilinxvc707pciex1 / XilinxVC707PCIeX1Periphery.scala

diff --git a/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala b/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala
index f37f7f9da272b571bcbfe2bdb4e89fb951d39200..008556a9a55d52d79c7caefe668be9ccdcebadda 100644 (file)
--- a/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala
+++ b/src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala
@@ -2,30 +2,35 @@
 package sifive.blocks.devices.xilinxvc707pciex1
 
 import Chisel._
-import diplomacy.LazyModule
-import rocketchip.{
-  HasTopLevelNetworks,
-  HasTopLevelNetworksModule,
-  HasTopLevelNetworksBundle
-}
-import uncore.tilelink2.TLWidthWidget
-
-trait HasPeripheryXilinxVC707PCIeX1 extends HasTopLevelNetworks {
+import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
+import freechips.rocketchip.chip.HasSystemNetworks
+import freechips.rocketchip.tilelink._
 
+trait HasPeripheryXilinxVC707PCIeX1 extends HasSystemNetworks {
   val xilinxvc707pcie = LazyModule(new XilinxVC707PCIeX1)
-  l2FrontendBus.node := xilinxvc707pcie.master
-  xilinxvc707pcie.slave   := TLWidthWidget(socBusConfig.beatBytes)(socBus.node)
-  xilinxvc707pcie.control := TLWidthWidget(socBusConfig.beatBytes)(socBus.node)
-  intBus.intnode := xilinxvc707pcie.intnode
+  private val intXing = LazyModule(new IntXing)
+
+  fsb.node := TLAsyncCrossingSink()(xilinxvc707pcie.master)
+  xilinxvc707pcie.slave   := TLAsyncCrossingSource()(TLWidthWidget(socBusConfig.beatBytes)(socBus.node))
+  xilinxvc707pcie.control := TLAsyncCrossingSource()(TLWidthWidget(socBusConfig.beatBytes)(socBus.node))
+  intBus.intnode := intXing.intnode
+  intXing.intnode := xilinxvc707pcie.intnode
 }
 
-trait HasPeripheryXilinxVC707PCIeX1Bundle extends HasTopLevelNetworksBundle {
-  val xilinxvc707pcie = new XilinxVC707PCIeX1IO
+trait HasPeripheryXilinxVC707PCIeX1Bundle {
+  val xilinxvc707pcie: XilinxVC707PCIeX1IO
+  def connectXilinxVC707PCIeX1ToPads(pads: XilinxVC707PCIeX1Pads) {
+    pads <> xilinxvc707pcie
+  }
 }
 
-trait HasPeripheryXilinxVC707PCIeX1Module extends HasTopLevelNetworksModule {
+trait HasPeripheryXilinxVC707PCIeX1ModuleImp extends LazyMultiIOModuleImp
+    with HasPeripheryXilinxVC707PCIeX1Bundle {
   val outer: HasPeripheryXilinxVC707PCIeX1
-  val io: HasPeripheryXilinxVC707PCIeX1Bundle
+  val xilinxvc707pcie = IO(new XilinxVC707PCIeX1IO)
+
+  xilinxvc707pcie <> outer.xilinxvc707pcie.module.io.port
 
-  io.xilinxvc707pcie <> outer.xilinxvc707pcie.module.io.port
+  outer.xilinxvc707pcie.module.clock := outer.xilinxvc707pcie.module.io.port.axi_aclk_out
+  outer.xilinxvc707pcie.module.reset := ~xilinxvc707pcie.axi_aresetn
 }