get fp mul pipe working using new FPNumBaseRecord

[ieee754fpu.git] / src / nmutil / concurrentunit.py

diff --git a/src/nmutil/concurrentunit.py b/src/nmutil/concurrentunit.py
index 5f02d7cd9ade7e11364c75aab2079bedd1fac57c..3d426ff9a7fe67f8969a9454ddf9cda365c61d97 100644 (file)
--- a/src/nmutil/concurrentunit.py
+++ b/src/nmutil/concurrentunit.py
@@ -9,7 +9,7 @@
 """
 
 from math import log
-from nmigen import Module
+from nmigen import Module, Elaboratable
 from nmigen.cli import main, verilog
 
 from nmutil.singlepipe import PassThroughStage
@@ -35,7 +35,7 @@ class FPADDMuxOutPipe(CombMuxOutPipe):
         CombMuxOutPipe.__init__(self, stage, n_len=self.num_rows)
 
 
-class ReservationStations:
+class ReservationStations(Elaboratable):
     """ Reservation-Station pipeline
 
         Input: num_rows - number of input and output Reservation Stations