use boolean version of SRLatch, suitable for multi-bit now

[ieee754fpu.git] / src / nmutil / latch.py

diff --git a/src/nmutil/latch.py b/src/nmutil/latch.py
index fd28cd4a3be9bb89e33c8f50c86ce57b44014eb7..cf41a0d38220f8a59b11c18c33fa93658059a5c8 100644 (file)
--- a/src/nmutil/latch.py
+++ b/src/nmutil/latch.py
@@ -43,24 +43,11 @@ class SRLatch(Elaboratable):
         m = Module()
         q_int = Signal()
 
+        m.d.sync += q_int.eq((q_int & ~self.r) | self.s)
         if self.sync:
-            with m.If(self.s):
-                m.d.sync += q_int.eq(1)
-            with m.Elif(self.r):
-                m.d.sync += q_int.eq(0)
-            with m.Else():
-                m.d.sync += q_int.eq(q_int)
             m.d.comb += self.q.eq(q_int)
         else:
-            with m.If(self.s):
-                m.d.sync += q_int.eq(1)
-                m.d.comb += self.q.eq(1)
-            with m.Elif(self.r):
-                m.d.sync += q_int.eq(0)
-                m.d.comb += self.q.eq(0)
-            with m.Else():
-                m.d.sync += q_int.eq(q_int)
-                m.d.comb += self.q.eq(q_int)
+            m.d.comb += self.q.eq((q_int & ~self.r) | self.s)
         m.d.comb += self.qn.eq(~self.q)
         m.d.comb += self.qlq.eq(self.q | q_int) # useful output