minor reorg of latch

[ieee754fpu.git] / src / nmutil / latch.py

diff --git a/src/nmutil/latch.py b/src/nmutil/latch.py
index 7c59b98395d733e32478c6a43d1760e912eea07d..dbdb23e55b76e660cec8a2c2b7ec80393147da7f 100644 (file)
--- a/src/nmutil/latch.py
+++ b/src/nmutil/latch.py
@@ -13,13 +13,14 @@ class SRLatch(Elaboratable):
     def elaborate(self, platform):
         m = Module()
         q_int = Signal(reset_less=True)
-        qn_int = Signal(reset_less=True)
 
-        m.d.comb += self.q.eq(~(self.s | qn_int))
-        m.d.comb += self.qn.eq(~(self.r | q_int))
+        with m.If(self.s):
+            m.d.sync += q_int.eq(1)
+        with m.Elif(self.r):
+            m.d.sync += q_int.eq(0)
 
-        m.d.sync += q_int.eq(self.q)
-        m.d.sync += qn_int.eq(self.qn)
+        m.d.comb += self.q.eq(q_int)
+        m.d.comb += self.qn.eq(~q_int)
 
         return m
 
@@ -31,15 +32,24 @@ def sr_sim(dut):
     yield dut.s.eq(0)
     yield dut.r.eq(0)
     yield
+    yield
+    yield
     yield dut.s.eq(1)
     yield
+    yield
+    yield
     yield dut.s.eq(0)
     yield
+    yield
+    yield
     yield dut.r.eq(1)
     yield
+    yield
+    yield
     yield dut.r.eq(0)
     yield
     yield
+    yield
 
 def test_sr():
     dut = SRLatch()