import ConcatReg::*;
import Semi_FIFOF::*;
import BUtils ::*;
- import AXI4_Lite_Types::*;
+ import AXI4_Types::*;
interface Ifc_rgbttl_dummy;
- interface AXI4_Lite_Slave_IFC#(`ADDR, `DATA, `USERSPACE) slave;
+ interface AXI4_Master_IFC#(`ADDR, `DATA, `USERSPACE) master;
interface Get#(Bit#(1)) de;
interface Get#(Bit#(1)) ck;
interface Get#(Bit#(1)) vs;
endmethod
endinterface;
- interface slave=s_xactor.axi_side;
+ interface master=s_xactor.axi_side;
endmodule
endpackage