use internal latch qlq value instead of creating a separate sync register

[soc.git] / src / scoreboard / fu_dep_cell.py

diff --git a/src/scoreboard/fu_dep_cell.py b/src/scoreboard/fu_dep_cell.py
index 544c3265882450fbb84c0bb51eba047f77b1ce65..4ac2a6daa76034c20339cb74bb2708259456e3eb 100644 (file)
--- a/src/scoreboard/fu_dep_cell.py
+++ b/src/scoreboard/fu_dep_cell.py
@@ -20,16 +20,12 @@ class DepCell(Elaboratable):
         m = Module()
         m.submodules.l = l = SRLatch(sync=False) # async latch
 
-        # record current version of q in a sync'd register
-        cq = Signal() # resets to 0
-        m.d.sync += cq.eq(l.q)
-
         # reset on go HI, set on dest and issue
         m.d.comb += l.s.eq(self.issue_i & self.pend_i)
         m.d.comb += l.r.eq(self.go_i)
 
         # wait out
-        m.d.comb += self.wait_o.eq((cq | l.q) & ~self.issue_i)
+        m.d.comb += self.wait_o.eq(l.qlq & ~self.issue_i)
 
         return m