make FU-FU DepCell a row

[soc.git] / src / scoreboard / fu_dep_cell.py

diff --git a/src/scoreboard/fu_dep_cell.py b/src/scoreboard/fu_dep_cell.py
index dc5daf39c1ad4edaf5b12b5fa2fcbe441d4fd214..9e97a7476628cf02e6a53114ba424ecdd1f012c8 100644 (file)
--- a/src/scoreboard/fu_dep_cell.py
+++ b/src/scoreboard/fu_dep_cell.py
@@ -4,38 +4,83 @@ from nmigen import Module, Signal, Elaboratable
 from nmutil.latch import SRLatch
 
 
+class DepCell(Elaboratable):
+    """ FU Dependency Cell
+    """
+    def __init__(self, llen=1):
+        self.llen = llen
+        # inputs
+        self.pend_i = Signal(llen, reset_less=True)    # pending bit in (left)
+        self.issue_i = Signal(llen, reset_less=True)   # Issue in (top)
+        self.go_i = Signal(llen, reset_less=True)      # Go read/write in (left)
+        self.die_i = Signal(llen, reset_less=True)     # Go die in (left)
+
+        # wait
+        self.wait_o = Signal(llen, reset_less=True)  # wait out (right)
+
+    def elaborate(self, platform):
+        m = Module()
+        m.submodules.l = l = SRLatch(sync=False, llen=self.llen) # async latch
+
+        # reset on go HI, set on dest and issue
+        m.d.comb += l.s.eq(self.issue_i & self.pend_i)
+        m.d.comb += l.r.eq(self.go_i | self.die_i)
+
+        # wait out
+        m.d.comb += self.wait_o.eq(l.qlq & ~self.issue_i)
+
+        return m
+
+    def __iter__(self):
+        yield self.pend_i
+        yield self.issue_i
+        yield self.go_i
+        yield self.die_i
+        yield self.wait_o
+
+    def ports(self):
+        return list(self)
+
+
 class FUDependenceCell(Elaboratable):
     """ implements 11.4.7 mitch alsup dependence cell, p27
     """
-    def __init__(self):
+    def __init__(self, n_fu=1):
+        self.n_fu = n_fu
         # inputs
-        self.rd_pend_i = Signal(reset_less=True)     # read pending in (left)
-        self.wr_pend_i = Signal(reset_less=True)     # write pending in (left)
-        self.issue_i = Signal(reset_less=True)    # Issue in (top)
+        self.rd_pend_i = Signal(n_fu, reset_less=True) # read pend in (left)
+        self.wr_pend_i = Signal(n_fu, reset_less=True) # write pend in (left)
+        self.issue_i = Signal(n_fu, reset_less=True)    # Issue in (top)
 
-        self.go_wr_i = Signal(reset_less=True) # Go Write in (left)
-        self.go_rd_i = Signal(reset_less=True)  # Go Read in (left)
+        self.go_wr_i = Signal(n_fu, reset_less=True) # Go Write in (left)
+        self.go_rd_i = Signal(n_fu, reset_less=True)  # Go Read in (left)
+        self.go_die_i = Signal(n_fu, reset_less=True) # Go Die in (left)
 
         # outputs (latched rd/wr wait)
-        self.rd_wait_o = Signal(reset_less=True)   # read waiting out (right)
-        self.wr_wait_o = Signal(reset_less=True)   # write waiting out (right)
+        self.rd_wait_o = Signal(n_fu, reset_less=True) # read wait out (right)
+        self.wr_wait_o = Signal(n_fu, reset_less=True) # write wait out (right)
 
     def elaborate(self, platform):
         m = Module()
-        m.submodules.rd_l = rd_l = SRLatch() # clock-sync'd
-        m.submodules.wr_l = wr_l = SRLatch() # clock-sync'd
+        m.submodules.rd_c = rd_c = DepCell(self.n_fu)
+        m.submodules.wr_c = wr_c = DepCell(self.n_fu)
+
+        # connect issue
+        for c in [rd_c, wr_c]:
+            m.d.comb += c.issue_i.eq(self.issue_i)
+            m.d.comb += c.die_i.eq(self.go_die_i)
 
-        # write latch: reset on go_wr HI, set on write waiting and issue
-        m.d.comb += wr_l.s.eq(self.issue_i & self.wr_pend_i)
-        m.d.comb += wr_l.r.eq(self.go_wr_i)
+        # connect go_rd / go_wr 
+        m.d.comb += wr_c.go_i.eq(self.go_wr_i)
+        m.d.comb += rd_c.go_i.eq(self.go_rd_i)
 
-        # read latch: reset on go_rd HI, set on read pending and issue
-        m.d.comb += rd_l.s.eq(self.issue_i & self.rd_pend_i)
-        m.d.comb += rd_l.r.eq(self.go_rd_i)
+        # connect pend_i
+        m.d.comb += wr_c.pend_i.eq(self.wr_pend_i)
+        m.d.comb += rd_c.pend_i.eq(self.rd_pend_i)
 
-        # Read/Write Pending Latches (read out horizontally)
-        m.d.comb += self.wr_wait_o.eq(wr_l.q)
-        m.d.comb += self.rd_wait_o.eq(rd_l.q)
+        # connect output
+        m.d.comb += self.wr_wait_o.eq(wr_c.wait_o)
+        m.d.comb += self.rd_wait_o.eq(rd_c.wait_o)
 
         return m
 
@@ -45,6 +90,7 @@ class FUDependenceCell(Elaboratable):
         yield self.issue_i
         yield self.go_wr_i
         yield self.go_rd_i
+        yield self.go_die_i
         yield self.rd_wait_o
         yield self.wr_wait_o