from nmigen.compat.sim import run_simulation
from nmigen.cli import verilog, rtlil
-from nmigen import Module, Signal, Elaboratable, Array, Cat
+from nmigen import Module, Signal, Elaboratable, Array, Cat, Const
#from nmutil.latch import SRLatch
-from fu_dep_cell import FUDependenceCell
-from fu_picker_vec import FU_Pick_Vec
+from .fu_dep_cell import FUDependenceCell
+from .fu_picker_vec import FU_Pick_Vec
"""
self.wr_pend_i = Signal(n_fu_row, reset_less=True) # Wr pending (left)
self.issue_i = Signal(n_fu_col, reset_less=True) # Issue in (top)
- self.go_write_i = Signal(n_fu_row, reset_less=True) # Go Write in (left)
- self.go_read_i = Signal(n_fu_row, reset_less=True) # Go Read in (left)
+ self.go_wr_i = Signal(n_fu_row, reset_less=True) # Go Write in (left)
+ self.go_rd_i = Signal(n_fu_row, reset_less=True) # Go Read in (left)
+ self.go_die_i = Signal(n_fu_row, reset_less=True) # Go Die in (left)
# for Function Unit Readable/Writable (horizontal)
self.readable_o = Signal(n_fu_col, reset_less=True) # readable (bot)
# ---
# matrix of dependency cells
# ---
- dm = Array(Array(FUDependenceCell() for r in range(self.n_fu_row)) \
+ dm = Array(FUDependenceCell(self.n_fu_row) \
for f in range(self.n_fu_col))
for x in range(self.n_fu_col):
- for y in range(self.n_fu_row):
- setattr(m.submodules, "dm_fx%d_fy%d" % (x, y), dm[x][y])
+ setattr(m.submodules, "dm%d" % x, dm[x])
# ---
# array of Function Unit Readable/Writable: row-length, horizontal
writable = []
for x in range(self.n_fu_col):
fu = fur[x]
- rd_pend_o = []
- wr_pend_o = []
- for y in range(self.n_fu_row):
- dc = dm[x][y]
- # accumulate cell outputs rd/wr-pending
- rd_pend_o.append(dc.rd_pend_o)
- wr_pend_o.append(dc.wr_pend_o)
- # connect cell reg-select outputs to Reg Vector In
- m.d.comb += [fu.rd_pend_i.eq(Cat(*rd_pend_o)),
- fu.wr_pend_i.eq(Cat(*wr_pend_o)),
- ]
# accumulate Readable/Writable Vector outputs
readable.append(fu.readable_o)
writable.append(fu.writable_o)
m.d.comb += self.writable_o.eq(Cat(*writable))
# ---
- # connect Dependency Matrix dest/src1/src2/issue to module d/s/s/i
+ # connect FU Pending
# ---
for y in range(self.n_fu_row):
- issue_i = []
+ fu = fur[y]
+ rd_wait_o = []
+ wr_wait_o = []
for x in range(self.n_fu_col):
- dc = dm[x][y]
+ dc = dm[x]
+ # accumulate cell outputs rd/wr-pending
+ rd_wait_o.append(dc.rd_wait_o[y])
+ wr_wait_o.append(dc.wr_wait_o[y])
+ # connect cell reg-select outputs to Reg Vector In
+ m.d.comb += [fu.rd_pend_i.eq(Cat(*rd_wait_o)),
+ fu.wr_pend_i.eq(Cat(*wr_wait_o)),
+ ]
+
+ # ---
+ # connect Dependency Matrix dest/src1/src2/issue to module d/s/s/i
+ # ---
+ for x in range(self.n_fu_col):
+ dc = dm[x]
+ issue_i = []
+ for y in range(self.n_fu_row):
# accumulate cell inputs issue
- issue_i.append(dc.issue_i)
+ issue_i.append(dc.issue_i[y])
# wire up inputs from module to row cell inputs (Cat is gooood)
m.d.comb += Cat(*issue_i).eq(self.issue_i)
# ---
- # connect Matrix go_read_i/go_write_i to module readable/writable
+ # connect Matrix go_rd_i/go_wr_i to module readable/writable
# ---
- for x in range(self.n_fu_col):
- go_read_i = []
- go_write_i = []
+ for y in range(self.n_fu_row):
+ go_rd_i = []
+ go_wr_i = []
+ go_die_i = []
+ for x in range(self.n_fu_col):
+ dc = dm[x]
+ # accumulate cell go_rd/go_wr
+ go_rd_i.append(dc.go_rd_i[y])
+ go_wr_i.append(dc.go_wr_i[y])
+ go_die_i.append(dc.go_die_i[y])
+ # wire up inputs from module to row cell inputs (Cat is gooood)
+ m.d.comb += [Cat(*go_rd_i).eq(self.go_rd_i),
+ Cat(*go_wr_i).eq(self.go_wr_i),
+ Cat(*go_die_i).eq(self.go_die_i),
+ ]
+
+
+ # ---
+ # connect Matrix pending
+ # ---
+ for y in range(self.n_fu_row):
rd_pend_i = []
wr_pend_i = []
- for y in range(self.n_fu_row):
- dc = dm[x][y]
- # accumulate cell rd_pend/wr_pend/go_read/go_write
- rd_pend_i.append(dc.rd_pend_i)
- wr_pend_i.append(dc.wr_pend_i)
- go_read_i.append(dc.go_read_i)
- go_write_i.append(dc.go_write_i)
+ for x in range(self.n_fu_col):
+ dc = dm[x]
+ if x == y: # ignore hazards on the diagonal: self-against-self
+ dummyrd = Signal(reset_less=True)
+ dummywr = Signal(reset_less=True)
+ rd_pend_i.append(dummyrd)
+ wr_pend_i.append(dummywr)
+ continue
+ # accumulate cell rd_pend/wr_pend/go_rd/go_wr
+ rd_pend_i.append(dc.rd_pend_i[y])
+ wr_pend_i.append(dc.wr_pend_i[y])
# wire up inputs from module to row cell inputs (Cat is gooood)
- m.d.comb += [Cat(*go_read_i).eq(self.go_read_i),
- Cat(*go_write_i).eq(self.go_write_i),
- Cat(*rd_pend_i).eq(self.rd_pend_i),
+ m.d.comb += [Cat(*rd_pend_i).eq(self.rd_pend_i),
Cat(*wr_pend_i).eq(self.wr_pend_i),
]
yield self.rd_pend_i
yield self.wr_pend_i
yield self.issue_i
- yield self.go_write_i
- yield self.go_read_i
+ yield self.go_wr_i
+ yield self.go_rd_i
yield self.readable_o
yield self.writable_o
yield
yield dut.issue_i.eq(0)
yield
- yield dut.go_read_i.eq(1)
+ yield dut.go_rd_i.eq(1)
yield
- yield dut.go_read_i.eq(0)
+ yield dut.go_rd_i.eq(0)
yield
- yield dut.go_write_i.eq(1)
+ yield dut.go_wr_i.eq(1)
yield
- yield dut.go_write_i.eq(0)
+ yield dut.go_wr_i.eq(0)
yield
def test_fu_fu_matrix():
projects / soc.git / blobdiff