rename v_rd_rsel_o in dependence cell as well

[soc.git] / src / scoreboard / fu_reg_matrix.py

diff --git a/src/scoreboard/fu_reg_matrix.py b/src/scoreboard/fu_reg_matrix.py
index f774fb9f544b0b49d439ee7b7f3e8cb441bdd84b..a578a9960e778c0e97d6561916e2772ba83caf1d 100644 (file)
--- a/src/scoreboard/fu_reg_matrix.py
+++ b/src/scoreboard/fu_reg_matrix.py
@@ -2,7 +2,6 @@ from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
 from nmigen import Module, Signal, Elaboratable, Array, Cat
 
-#from nmutil.latch import SRLatch
 from scoreboard.dependence_cell import DependencyRow
 from scoreboard.fu_wr_pending import FU_RW_Pend
 from scoreboard.reg_select import Reg_Rsv
@@ -39,8 +38,8 @@ class FURegDepMatrix(Elaboratable):
         # Register "Global" vectors for determining RaW and WaR hazards
         self.wr_pend_i = Signal(n_reg_col, reset_less=True) # wr pending (top)
         self.rd_pend_i = Signal(n_reg_col, reset_less=True) # rd pending (top)
-        self.wr_rsel_o = Signal(n_reg_col, reset_less=True) # wr pending (bot)
-        self.rd_rsel_o = Signal(n_reg_col, reset_less=True) # rd pending (bot)
+        self.v_wr_rsel_o = Signal(n_reg_col, reset_less=True) # wr pending (bot)
+        self.v_rd_rsel_o = Signal(n_reg_col, reset_less=True) # rd pending (bot)
 
         self.issue_i = Signal(n_fu_row, reset_less=True)  # Issue in (top)
         self.go_wr_i = Signal(n_fu_row, reset_less=True)  # Go Write in (left)
@@ -167,15 +166,15 @@ class FURegDepMatrix(Elaboratable):
         wr_pend_v = []
         for fu in range(self.n_fu_row):
             dc = dm[fu]
-            rd_pend_v.append(dc.rd_rsel_o)
-            wr_pend_v.append(dc.wr_rsel_o)
+            rd_pend_v.append(dc.v_rd_rsel_o)
+            wr_pend_v.append(dc.v_wr_rsel_o)
         rd_v = GlobalPending(self.n_reg_col, rd_pend_v)
         wr_v = GlobalPending(self.n_reg_col, wr_pend_v)
         m.submodules.rd_v = rd_v
         m.submodules.wr_v = wr_v
 
-        m.d.comb += self.rd_rsel_o.eq(rd_v.g_pend_o)
-        m.d.comb += self.wr_rsel_o.eq(wr_v.g_pend_o)
+        m.d.comb += self.v_rd_rsel_o.eq(rd_v.g_pend_o)
+        m.d.comb += self.v_wr_rsel_o.eq(wr_v.g_pend_o)
 
         # ---
         # connect Dep issue_i/go_rd_i/go_wr_i to module issue_i/go_rd/go_wr
@@ -215,8 +214,8 @@ class FURegDepMatrix(Elaboratable):
         yield self.rd_pend_o
         yield self.wr_pend_i
         yield self.rd_pend_i
-        yield self.wr_rsel_o
-        yield self.rd_rsel_o
+        yield self.v_wr_rsel_o
+        yield self.v_rd_rsel_o
         yield self.rd_src1_pend_o
         yield self.rd_src2_pend_o