from nmigen.cli import verilog, rtlil
from nmigen import Module, Signal, Elaboratable, Array, Cat
-#from nmutil.latch import SRLatch
from scoreboard.dependence_cell import DependencyRow
from scoreboard.fu_wr_pending import FU_RW_Pend
from scoreboard.reg_select import Reg_Rsv
+from scoreboard.global_pending import GlobalPending
"""
6600 Dependency Table Matrix inputs / outputs
---------------------------------------------
- d s1 s2 i d s1 s2 i d s1 s2 i d s1 s2 i
- | | | | | | | | | | | | | | | |
- v v v v v v v v v v v v v v v v
+ d s1 s2 i d s1 s2 i d s1 s2 i d s1 s2 i
+ | | | | | | | | | | | | | | | |
+ v v v v v v v v v v v v v v v v
go_rd/go_wr -> dm-r0-fu0 dm-r1-fu0 dm-r2-fu0 dm-r3-fu0 -> wr/rd-pend
go_rd/go_wr -> dm-r0-fu1 dm-r1-fu1 dm-r2-fu1 dm-r3-fu1 -> wr/rd-pend
go_rd/go_wr -> dm-r0-fu2 dm-r1-fu2 dm-r2-fu2 dm-r3-fu2 -> wr/rd-pend
self.src1_i = Signal(n_reg_col, reset_less=True) # oper1 in (top)
self.src2_i = Signal(n_reg_col, reset_less=True) # oper2 in (top)
- self.issue_i = Signal(n_fu_row, reset_less=True) # Issue in (top)
- self.go_wr_i = Signal(n_fu_row, reset_less=True) # Go Write in (left)
+ # Register "Global" vectors for determining RaW and WaR hazards
+ self.wr_pend_i = Signal(n_reg_col, reset_less=True) # wr pending (top)
+ self.rd_pend_i = Signal(n_reg_col, reset_less=True) # rd pending (top)
+ self.v_wr_rsel_o = Signal(n_reg_col, reset_less=True) # wr pending (bot)
+ self.v_rd_rsel_o = Signal(n_reg_col, reset_less=True) # rd pending (bot)
+
+ self.issue_i = Signal(n_fu_row, reset_less=True) # Issue in (top)
+ self.go_wr_i = Signal(n_fu_row, reset_less=True) # Go Write in (left)
self.go_rd_i = Signal(n_fu_row, reset_less=True) # Go Read in (left)
+ self.go_die_i = Signal(n_fu_row, reset_less=True) # Go Die in (left)
# for Register File Select Lines (horizontal), per-reg
self.dest_rsel_o = Signal(n_reg_col, reset_less=True) # dest reg (bot)
src1_fwd_o = []
src2_fwd_o = []
for rn in range(self.n_reg_col):
- # accumulate cell fwd outputs for dest/src1/src2
+ # accumulate cell fwd outputs for dest/src1/src2
dest_fwd_o.append(dc.dest_fwd_o[rn])
src1_fwd_o.append(dc.src1_fwd_o[rn])
src2_fwd_o.append(dc.src2_fwd_o[rn])
m.d.comb += self.rd_src1_pend_o.eq(Cat(*rd_src1_pend))
m.d.comb += self.rd_src2_pend_o.eq(Cat(*rd_src2_pend))
- print ("wr pend len", len(wr_pend))
-
# ---
# connect Reg Selection vector
# ---
src2_rsel = []
for rn in range(self.n_reg_col):
rsv = regrsv[rn]
+ dest_rsel_o = []
+ src1_rsel_o = []
+ src2_rsel_o = []
+ for fu in range(self.n_fu_row):
+ dc = dm[fu]
+ # accumulate cell reg-select outputs dest/src1/src2
+ dest_rsel_o.append(dc.dest_rsel_o[rn])
+ src1_rsel_o.append(dc.src1_rsel_o[rn])
+ src2_rsel_o.append(dc.src2_rsel_o[rn])
# connect cell reg-select outputs to Reg Vector In
- m.d.comb += [rsv.dest_rsel_i.eq(dc.dest_rsel_o),
- rsv.src1_rsel_i.eq(dc.src1_rsel_o),
- rsv.src2_rsel_i.eq(dc.src2_rsel_o),
+ m.d.comb += [rsv.dest_rsel_i.eq(Cat(*dest_rsel_o)),
+ rsv.src1_rsel_i.eq(Cat(*src1_rsel_o)),
+ rsv.src2_rsel_i.eq(Cat(*src2_rsel_o)),
]
# accumulate Reg-Sel Vector outputs
dest_rsel.append(rsv.dest_rsel_o)
src1_rsel.append(rsv.src1_rsel_o)
src2_rsel.append(rsv.src2_rsel_o)
- print ("dest_rsel_rsv len", len(rsv.dest_rsel_o))
# ... and output them from this module (horizontal, width=REGs)
m.d.comb += self.dest_rsel_o.eq(Cat(*dest_rsel))
m.d.comb += self.src1_rsel_o.eq(Cat(*src1_rsel))
m.d.comb += self.src2_rsel_o.eq(Cat(*src2_rsel))
- print ("dest rsel len", len(dest_rsel), self.dest_rsel_o)
# ---
# connect Dependency Matrix dest/src1/src2/issue to module d/s/s/i
# ---
m.d.comb += [dc.dest_i.eq(self.dest_i),
dc.src1_i.eq(self.src1_i),
dc.src2_i.eq(self.src2_i),
+ dc.rd_pend_i.eq(self.rd_pend_i),
+ dc.wr_pend_i.eq(self.wr_pend_i),
]
+ # accumulate rsel bits into read/write pending vectors.
+ rd_pend_v = []
+ wr_pend_v = []
+ for fu in range(self.n_fu_row):
+ dc = dm[fu]
+ rd_pend_v.append(dc.v_rd_rsel_o)
+ wr_pend_v.append(dc.v_wr_rsel_o)
+ rd_v = GlobalPending(self.n_reg_col, rd_pend_v)
+ wr_v = GlobalPending(self.n_reg_col, wr_pend_v)
+ m.submodules.rd_v = rd_v
+ m.submodules.wr_v = wr_v
+
+ m.d.comb += self.v_rd_rsel_o.eq(rd_v.g_pend_o)
+ m.d.comb += self.v_wr_rsel_o.eq(wr_v.g_pend_o)
+
# ---
# connect Dep issue_i/go_rd_i/go_wr_i to module issue_i/go_rd/go_wr
# ---
- for rn in range(self.n_reg_col):
- go_rd_i = []
- go_wr_i = []
- issue_i = []
- for fu in range(self.n_fu_row):
- dc = dm[fu]
- # accumulate cell fwd outputs for dest/src1/src2
- go_rd_i.append(dc.go_rd_i[rn])
- go_wr_i.append(dc.go_wr_i[rn])
- issue_i.append(dc.issue_i[rn])
- # wire up inputs from module to row cell inputs (Cat is gooood)
- m.d.comb += [Cat(*go_rd_i).eq(self.go_rd_i),
- Cat(*go_wr_i).eq(self.go_wr_i),
- Cat(*issue_i).eq(self.issue_i),
- ]
+ go_rd_i = []
+ go_wr_i = []
+ go_die_i = []
+ issue_i = []
+ for fu in range(self.n_fu_row):
+ dc = dm[fu]
+ # accumulate cell fwd outputs for dest/src1/src2
+ go_rd_i.append(dc.go_rd_i)
+ go_wr_i.append(dc.go_wr_i)
+ go_die_i.append(dc.go_die_i)
+ issue_i.append(dc.issue_i)
+ # wire up inputs from module to row cell inputs (Cat is gooood)
+ m.d.comb += [Cat(*go_rd_i).eq(self.go_rd_i),
+ Cat(*go_wr_i).eq(self.go_wr_i),
+ Cat(*go_die_i).eq(self.go_die_i),
+ Cat(*issue_i).eq(self.issue_i),
+ ]
return m
yield self.issue_i
yield self.go_wr_i
yield self.go_rd_i
+ yield self.go_die_i
yield self.dest_rsel_o
yield self.src1_rsel_o
yield self.src2_rsel_o
yield self.wr_pend_o
yield self.rd_pend_o
+ yield self.wr_pend_i
+ yield self.rd_pend_i
+ yield self.v_wr_rsel_o
+ yield self.v_rd_rsel_o
yield self.rd_src1_pend_o
yield self.rd_src2_pend_o
-
+
def ports(self):
return list(self)
projects / soc.git / blobdiff