almost all tests work

[soc.git] / src / soc / TLB / ariane / test / test_ptw.py

diff --git a/src/soc/TLB/ariane/test/test_ptw.py b/src/soc/TLB/ariane/test/test_ptw.py
index b5deb28b5ab607eb6a9a2f4543585683dd998f23..396975664c12069b10284620cc2d401a8c3e456a 100644 (file)
--- a/src/soc/TLB/ariane/test/test_ptw.py
+++ b/src/soc/TLB/ariane/test/test_ptw.py
@@ -1,24 +1,20 @@
-import sys
-sys.path.append("../src")
-sys.path.append("../../../TestUtil")
-
 from nmigen.compat.sim import run_simulation
-
-from TLB.ariane.ptw import PTW, PTE
+from soc.TLB.ariane.ptw import PTW, PTE
 
 # unit was changed, test needs to be changed
 
+
 def tbench(dut):
 
     addr = 0x8000000
 
     #pte = PTE()
-    #yield pte.v.eq(1)
-    #yield pte.r.eq(1)
+    # yield pte.v.eq(1)
+    # yield pte.r.eq(1)
 
     yield dut.req_port_i.data_gnt.eq(1)
     yield dut.req_port_i.data_rvalid.eq(1)
-    yield dut.req_port_i.data_rdata.eq(0x43)#pte.flatten())
+    yield dut.req_port_i.data_rdata.eq(0x43)  # pte.flatten())
 
     # data lookup
     yield dut.en_ld_st_translation_i.eq(1)
@@ -56,7 +52,8 @@ def tbench(dut):
     yield dut.mxr_i.eq(0x1)
     yield dut.req_port_i.data_gnt.eq(1)
     yield dut.req_port_i.data_rvalid.eq(1)
-    yield dut.req_port_i.data_rdata.eq(0x41 | (addr>>12)<<10)#pte.flatten())
+    # pte.flatten())
+    yield dut.req_port_i.data_rdata.eq(0x41 | (addr >> 12) << 10)
 
     yield dut.en_ld_st_translation_i.eq(1)
     yield dut.asid_i.eq(1)
@@ -86,7 +83,6 @@ def tbench(dut):
     yield
     yield
 
-
     # instruction lookup
     yield dut.en_ld_st_translation_i.eq(0)
     yield dut.enable_translation_i.eq(1)
@@ -126,5 +122,6 @@ def test_ptw():
     run_simulation(dut, tbench(dut), vcd_name="test_ptw.vcd")
     print("PTW Unit Test Success")
 
+
 if __name__ == "__main__":
     test_ptw()