add QTY 4of 4k SRAMs SPBlock512W64B8W to TestIssuer if enabled

[soc.git] / src / soc / bus / SPBlock512W64B8W.py

diff --git a/src/soc/bus/SPBlock512W64B8W.py b/src/soc/bus/SPBlock512W64B8W.py
index aa7fe20a24c2b610befed6f34687057a9f134e43..d86b237508152d9555fb8317d929e84fd605e74f 100644 (file)
--- a/src/soc/bus/SPBlock512W64B8W.py
+++ b/src/soc/bus/SPBlock512W64B8W.py
@@ -12,7 +12,7 @@ class SPBlock512W64B8W(Elaboratable):
     Instance SPBlock512W64B8W).  512 rows, 64-bit, QTY 8 write-enable lines
     """
 
-    def __init__(self, bus=None, features=None):
+    def __init__(self, bus=None, features=None, name=None):
         if features is None:
             features = frozenset()
         if bus is None:
@@ -21,7 +21,7 @@ class SPBlock512W64B8W(Elaboratable):
                             granularity=8, # at 8-bit granularity
                             features=features,
                             alignment=0,
-                            name=None)
+                            name=name)
         self.bus = bus
         self.granularity = bus.granularity