"""
def __init__(self, *, sys_clk_freq=100e6,
+ spi_offset=None,
+ dram_addr=None,
has_uart=True,
uart_is_16550=True
):
super().__init__(name="syscon")
self.sys_clk_freq = sys_clk_freq
self.has_uart = has_uart
+ self.spi_offset = spi_offset
+ self.dram_addr = dram_addr
self.uart_is_16550 = uart_is_16550
# System control ports
# system clock rate (hz)
comb += self._clk_info_r.r_data.eq(int(self.sys_clk_freq)) # in hz
+ # detect peripherals
+ has_spi = self.spi_offset is not None
+ has_dram = self.dram_addr is not None
+
# uart peripheral clock rate, currently assumed to be system clock
# 0 ..31 : UART clock freq (in HZ)
# 32 : UART is 16550 (otherwise pp)
- if self.has_uart:
- comb += self._uart0_info_r.r_data[0:32].eq(int(self.sys_clk_freq))
- comb += self._uart0_info_r.r_data[32].eq(1)
+ comb += self._uart0_info_r.r_data[0:32].eq(int(self.sys_clk_freq))
+ comb += self._uart0_info_r.r_data[32].eq(1)
+
+ # Reg Info, defines what peripherals and characteristics are present
+ comb += self._reg_info_r.r_data[0].eq(self.has_uart) # has UART0
+ comb += self._reg_info_r.r_data[1].eq(has_dram # has DDR DRAM
+ comb += self._reg_info_r.r_data[3].eq(has_spi) # has SPI Flash
+ comb += self._reg_info_r.r_data[5].eq(1) # Large SYSCON
# system control
sysctrl = Cat(self.dram_at_0, self.core_reset, self.soc_reset)
sync += sysctrl.eq(self._ctrl_info_r.w_data)
comb += self._ctrl_info_r.r_data.eq(sysctrl)
+ # SPI Flash Address
+ comb += self._spiflash_info_r.r_data.eq(self.spi_offset or 0)
+
return m
m = Module()
arbiter = wishbone.Arbiter(addr_width=30, data_width=32,
granularity=8)
- decoder = wishbone.Decoder(addr_width=30, data_width=32,
+ decoder = wishbone.Decoder(addr_width=30, data_width=32,
granularity=8)
m.submodules.syscon = syscon = MicrowattSYSCON()
m.submodules.decoder = decoder