self.specials does not exist, Instances must be added as submodules

[soc.git] / src / soc / bus / tercel.py

diff --git a/src/soc/bus/tercel.py b/src/soc/bus/tercel.py
index c7d550ed0c28304d7d2be565171549bc5812237a..1e204b5a582516dabfd7a41b8544b2cc8bbef029 100644 (file)
--- a/src/soc/bus/tercel.py
+++ b/src/soc/bus/tercel.py
@@ -120,9 +120,9 @@ class Tercel(Elaboratable):
 
                             # SPI region Wishbone bus signals
                             i_wishbone_adr=spi_bus_adr,
-                            i_wishbone_dat=bus.dat_w,
+                            i_wishbone_dat_w=bus.dat_w,
                             i_wishbone_sel=bus.sel,
-                            o_wishbone_dat=bus.dat_r,
+                            o_wishbone_dat_r=bus.dat_r,
                             i_wishbone_we=bus.we,
                             i_wishbone_stb=bus.stb,
                             i_wishbone_cyc=bus.cyc,
@@ -130,9 +130,9 @@ class Tercel(Elaboratable):
 
                             # Configuration region Wishbone bus signals
                             i_cfg_wishbone_adr=cfg_bus.adr,
-                            i_cfg_wishbone_dat=cfg_bus.dat_w,
+                            i_cfg_wishbone_dat_w=cfg_bus.dat_w,
                             i_cfg_wishbone_sel=cfg_bus.sel,
-                            o_cfg_wishbone_dat=cfg_bus.dat_r,
+                            o_cfg_wishbone_dat_r=cfg_bus.dat_r,
                             i_cfg_wishbone_we=cfg_bus.we,
                             i_cfg_wishbone_stb=cfg_bus.stb,
                             i_cfg_wishbone_cyc=cfg_bus.cyc,
@@ -162,7 +162,7 @@ class Tercel(Elaboratable):
             comb += pins.cs.eq(~self.cs_n_out)
             # ECP5 needs special handling for the SPI clock, sigh.
             if self.lattice_ecp5_usrmclk:
-                self.specials += Instance("USRMCLK",
+                m.submodules += Instance("USRMCLK",
                     i_USRMCLKI  = self.spi_clk,
                     i_USRMCLKTS = 0
                 )