# this is a wrapper around the opencores verilog tercel module
from nmigen import (Elaboratable, Cat, Module, Signal, ClockSignal, Instance,
- ResetSignal)
+ ResetSignal, Const)
from nmigen_soc.wishbone.bus import Interface
from nmigen_soc.memory import MemoryMap
def __init__(self, bus=None, cfg_bus=None, features=None, name=None,
data_width=32, spi_region_addr_width=28, pins=None,
clk_freq=None,
- lattice_ecp5_usrmclk=False):
+ lattice_ecp5_usrmclk=False,
+ adr_offset=0): # address offset (bytes)
if name is not None:
# convention: give the name in the format "name_number"
self.idx = int(name.split("_")[-1])
self.granularity = 8
self.data_width = data_width
self.dsize = log2_int(self.data_width//self.granularity)
+ self.adr_offset = adr_offset
+ self.lattice_ecp5_usrmclk = lattice_ecp5_usrmclk
+
+ # TODO, sort this out.
+ assert clk_freq is not None
+ clk_freq = round(clk_freq)
+ self.clk_freq = Const(clk_freq, clk_freq.bit_length())
# set up the wishbone busses
if features is None:
self.dq_in = Signal(4)
self.cs_n_out = Signal() # Slave select
self.spi_clk = Signal() # Clock
+ self.dbg_port = Signal(8) # debug info
# pins resource
self.pins = pins
def elaborate(self, platform):
m = Module()
comb = m.d.comb
+ pins, bus, cfg_bus = self.pins, self.bus, self.cfg_bus
# Calculate SPI flash address
spi_bus_adr = Signal(30)
# wb address is in words, offset is in bytes
- comb += spi_bus_adr.eq(bus.adr - (adr_offset >> 2))
+ comb += spi_bus_adr.eq(bus.adr - (self.adr_offset >> 2))
# create definition of external verilog Tercel code here, so that
# nmigen understands I/O directions (defined by i_ and o_ prefixes)
idx, bus = self.idx, self.bus
tercel = Instance("tercel_core",
# System parameters
- i_sys_clk_freq = clk_freq,
+ i_sys_clk_freq = self.clk_freq,
# Clock/reset (use DomainRenamer if needed)
i_peripheral_clock=ClockSignal(),
i_peripheral_reset=ResetSignal(),
# SPI region Wishbone bus signals
- i_wishbone_adr_i=spi_bus_adr,
- i_wishbone_dat_i=bus.dat_w,
- i_wishbone_sel_i=bus.sel,
- o_wishbone_dat_o=bus.dat_r,
- i_wishbone_we_i=bus.we,
- i_wishbone_stb_i=bus.stb,
- i_wishbone_cyc_i=bus.cyc,
- o_wishbone_ack_o=bus.ack,
+ i_wishbone_adr=spi_bus_adr,
+ i_wishbone_dat_w=bus.dat_w,
+ i_wishbone_sel=bus.sel,
+ o_wishbone_dat_r=bus.dat_r,
+ i_wishbone_we=bus.we,
+ i_wishbone_stb=bus.stb,
+ i_wishbone_cyc=bus.cyc,
+ o_wishbone_ack=bus.ack,
# Configuration region Wishbone bus signals
- i_cfg_wishbone_adr_i=cfg_bus.adr,
- i_cfg_wishbone_dat_i=cfg_bus.dat_w,
- i_cfg_wishbone_sel_i=cfg_bus.sel,
- o_cfg_wishbone_dat_o=cfg_bus.dat_r,
- i_cfg_wishbone_we_i=cfg_bus.we,
- i_cfg_wishbone_stb_i=cfg_bus.stb,
- i_cfg_wishbone_cyc_i=cfg_bus.cyc,
- o_cfg_wishbone_ack_o=cfg_bus.ack,
+ i_cfg_wishbone_adr=cfg_bus.adr,
+ i_cfg_wishbone_dat_w=cfg_bus.dat_w,
+ i_cfg_wishbone_sel=cfg_bus.sel,
+ o_cfg_wishbone_dat_r=cfg_bus.dat_r,
+ i_cfg_wishbone_we=cfg_bus.we,
+ i_cfg_wishbone_stb=cfg_bus.stb,
+ i_cfg_wishbone_cyc=cfg_bus.cyc,
+ o_cfg_wishbone_ack=cfg_bus.ack,
# QSPI signals
o_spi_d_out=self.dq_out,
o_spi_d_direction=self.dq_direction,
i_spi_d_in=self.dq_in,
o_spi_ss_n=self.cs_n_out,
- o_spi_clock=self.spi_clk
- );
+ o_spi_clock=self.spi_clk,
- m.submodules['tercel_%d' % self.idx] = uart
+ # debug port
+ o_debug_port=self.dbg_port
+ );
- if self.pins is not None:
- comb += self.pins.dq.o.eq(self.dq_out)
- comb += self.pins.dq.oe.eq(self.dq_direction)
- comb += self.pins.dq.oe.eq(self.dq_direction)
- comb += self.pins.dq.o_clk.eq(ClockSignal())
- comb += self.dq_in.eq(self.pins.dq.i)
- comb += self.pins.dq.i_clk.eq(ClockSignal())
- comb += self.pins.cs_n.eq(self.cs_n_out)
+ m.submodules['tercel_%d' % self.idx] = tercel
+
+ if pins is not None:
+ comb += pins.dq.o.eq(self.dq_out)
+ comb += pins.dq.oe.eq(self.dq_direction)
+ comb += pins.dq.oe.eq(self.dq_direction)
+ comb += pins.dq.o_clk.eq(ClockSignal())
+ comb += self.dq_in.eq(pins.dq.i)
+ comb += pins.dq.i_clk.eq(ClockSignal())
+ # XXX invert handled by SPIFlashResource
+ comb += pins.cs.eq(~self.cs_n_out)
# ECP5 needs special handling for the SPI clock, sigh.
- if lattice_ecp5_usrmclk:
+ if self.lattice_ecp5_usrmclk:
self.specials += Instance("USRMCLK",
i_USRMCLKI = self.spi_clk,
i_USRMCLKTS = 0
)
else:
- comb += pads.clk.eq(self.spi_clk)
+ comb += pins.clk.eq(self.spi_clk)
return m
+ def ports(self):
+ return [self.bus.cyc, self.bus.stb, self.bus.ack,
+ self.bus.dat_r, self.bus.dat_w, self.bus.adr,
+ self.bus.we, self.bus.sel,
+ self.cfg_bus.cyc, self.cfg_bus.stb,
+ self.cfg_bus.ack,
+ self.cfg_bus.dat_r, self.cfg_bus.dat_w,
+ self.cfg_bus.adr,
+ self.cfg_bus.we, self.cfg_bus.sel,
+ self.dq_out, self.dq_direction, self.dq_in,
+ self.cs_n_out, self.spi_clk
+ ]
+
def create_ilang(dut, ports, test_name):
vl = rtlil.convert(dut, name=test_name, ports=ports)
if __name__ == "__main__":
- tercel = Tercel(name="spi_0", data_width=32)
- create_ilang(tercel, [tercel.bus.cyc, tercel.bus.stb, tercel.bus.ack,
- tercel.bus.dat_r, tercel.bus.dat_w, tercel.bus.adr,
- tercel.bus.we, tercel.bus.sel,
- tercel.cfg_bus.cyc, tercel.cfg_bus.stb,
- tercel.cfg_bus.ack,
- tercel.cfg_bus.dat_r, tercel.cfg_bus.dat_w,
- tercel.cfg_bus.adr,
- tercel.cfg_bus.we, tercel.cfg_bus.sel,
- tercel.dq_out, tercel.dq_direction, tercel.dq_in,
- tercel.cs_n_out, tercel.spi_clk
- ], "spi_0")
+ tercel = Tercel(name="spi_0", data_width=32, clk_freq=100e6)
+ create_ilang(tercel, tercel.ports(), "spi_0")
projects / soc.git / blobdiff