from nmigen_soc.wishbone.bus import Interface
from nmigen.cli import rtlil, verilog
import os
+import tempfile
__all__ = ["UART16550"]
UART16550.add_verilog_source
"""
- def __init__(self, bus=None, features=None, name=None, data_width=32):
+ def __init__(self, bus=None, features=None, name=None, data_width=32,
+ pins=None, irq=None):
if name is not None:
# convention: give the name in the format "name_number"
self.idx = int(name.split("_")[-1])
else:
self.idx = 0
name = "uart_0"
+ self.data_width = data_width
# set up the wishbone bus
if features is None:
"bus width must be %d" % data_width
# IRQ for data buffer receive/xmit
- self.irq = Signal()
+ if irq is None:
+ irq = Signal()
+ self.irq = irq
# 9-pin UART signals (if anyone still remembers those...)
self.tx_o = Signal() # transmit
self.ri_i = Signal() # can't even remember what this is!
self.dcd_i = Signal() # or this!
+ # pins resource
+ self.pins = pins
+
@classmethod
def add_verilog_source(cls, verilog_src_dir, platform):
+ # create a temp file containing "`define DATA_BUS_WIDTH_8"
+ t = tempfile.NamedTemporaryFile(delete=False, suffix=".v")
+ t.write("`define DATA_BUS_WIDTH_8\n".encode())
+ t.flush()
+ t.seek(0)
+ platform.add_file(t.name, t)
+
# add each of the verilog sources, needed for when doing platform.build
for fname in ['raminfr.v', 'uart_defines.v', 'uart_rfifo.v',
'uart_top.v', 'timescale.v', 'uart_receiver.v',
def elaborate(self, platform):
m = Module()
+ comb = m.d.comb
# create definition of external verilog 16550 uart here, so that # nmigen understands I/O directions (defined by i_ and o_ prefixes)
idx, bus = self.idx, self.bus
m.submodules['uart16550_%d' % self.idx] = uart
+ if self.pins is not None:
+ comb += self.pins.tx.eq(self.tx_o)
+ comb += self.rx_i.eq(self.pins.rx)
+
return m