add tempfile to uart16550 wrapper which defines DATA_BUS_WIDTH_8

[soc.git] / src / soc / bus / uart_16550.py

diff --git a/src/soc/bus/uart_16550.py b/src/soc/bus/uart_16550.py
index 87779a53895e0af5571e099fa3d027cab8185c3b..bceec5e29249b0048f0d0ca936b5b10243cc7505 100644 (file)
--- a/src/soc/bus/uart_16550.py
+++ b/src/soc/bus/uart_16550.py
@@ -13,6 +13,7 @@ from nmigen import (Elaboratable, Cat, Module, Signal, ClockSignal, Instance,
 from nmigen_soc.wishbone.bus import Interface
 from nmigen.cli import rtlil, verilog
 import os
+import tempfile
 
 __all__ = ["UART16550"]
 
@@ -22,25 +23,28 @@ class UART16550(Elaboratable):
        UART16550.add_verilog_source
     """
 
-    def __init__(self, bus=None, features=None, name=None):
+    def __init__(self, bus=None, features=None, name=None, data_width=32,
+                       pins=None):
         if name is not None:
             # convention: give the name in the format "name_number"
             self.idx = int(name.split("_")[-1])
         else:
             self.idx = 0
             name = "uart_0"
+        self.data_width = data_width
 
         # set up the wishbone bus
         if features is None:
             features = frozenset()
         if bus is None:
             bus = Interface(addr_width=5,
-                            data_width=32,
+                            data_width=data_width,
                             features=features,
                             granularity=8,
                             name=name+"_wb_%d" % self.idx)
         self.bus = bus
-        assert len(self.bus.dat_r) == 32, "bus width must be 32"
+        assert len(self.bus.dat_r) == data_width, \
+                        "bus width must be %d" % data_width
 
         # IRQ for data buffer receive/xmit
         self.irq = Signal() 
@@ -55,8 +59,18 @@ class UART16550(Elaboratable):
         self.ri_i = Signal() # can't even remember what this is!
         self.dcd_i = Signal() # or this!
 
+        # pins resource
+        self.pins = pins
+
     @classmethod
     def add_verilog_source(cls, verilog_src_dir, platform):
+        # create a temp file containing "`define DATA_BUS_WIDTH_8"
+        t = tempfile.NamedTemporaryFile(delete=False, suffix=".v")
+        t.write("`define DATA_BUS_WIDTH_8\n".encode())
+        t.flush()
+        t.seek(0)
+        platform.add_file(t.name, t)
+
         # add each of the verilog sources, needed for when doing platform.build
         for fname in ['raminfr.v', 'uart_defines.v', 'uart_rfifo.v',
                       'uart_top.v', 'timescale.v', 'uart_receiver.v',
@@ -71,6 +85,7 @@ class UART16550(Elaboratable):
 
     def elaborate(self, platform):
         m = Module()
+        comb = m.d.comb
 
         # create definition of external verilog 16550 uart here, so that                # nmigen understands I/O directions (defined by i_ and o_ prefixes)
         idx, bus = self.idx, self.bus
@@ -102,6 +117,10 @@ class UART16550(Elaboratable):
 
         m.submodules['uart16550_%d' % self.idx] = uart
 
+        if self.pins is not None:
+            comb += self.pins.tx.eq(self.tx_o)
+            comb += self.rx_i.eq(self.pins.rx)
+
         return m
 
 
@@ -117,7 +136,7 @@ def create_verilog(dut, ports, test_name):
 
 
 if __name__ == "__main__":
-    uart = UART16550(name="uart_0")
+    uart = UART16550(name="uart_0", data_width=8)
     create_ilang(uart, [uart.bus.cyc, uart.bus.stb, uart.bus.ack,
                         uart.bus.dat_r, uart.bus.dat_w, uart.bus.adr,
                         uart.bus.we, uart.bus.sel,