select width is data_width // data granularity.

[soc.git] / src / soc / bus / wb_async.py

diff --git a/src/soc/bus/wb_async.py b/src/soc/bus/wb_async.py
index 2df49351a0dbfbd06b7a0f08a1fc77d5511ce84b..9c7b4e2ced24ed9eaddad11b7fa123e8dc6c7cf2 100644 (file)
--- a/src/soc/bus/wb_async.py
+++ b/src/soc/bus/wb_async.py
@@ -25,7 +25,8 @@ class WBAsyncBridge(Elaboratable):
     remember to call WBAsyncBridge.add_verilog_source
     """
 
-    def __init__(self, master_bus=None, slave_bus=None, features=None, name=None,
+    def __init__(self, master_bus=None, slave_bus=None, master_features=None,
+                       slave_features=None, name=None,
                        address_width=30, data_width=32, granularity=8,
                        master_clock_domain=None, slave_clock_domain=None):
         if name is not None:
@@ -54,18 +55,20 @@ class WBAsyncBridge(Elaboratable):
             self.wb_srst = ResetSignal(slave_clock_domain)
 
         # set up the wishbone busses
-        if features is None:
-            features = frozenset()
+        if master_features is None:
+            master_features = frozenset()
+        if slave_features is None:
+            slave_features = frozenset()
         if master_bus is None:
             master_bus = Interface(addr_width=self.address_width,
                             data_width=self.data_width,
-                            features=features,
+                            features=master_features,
                             granularity=self.granularity,
                             name=name+"_wb_%d_master" % self.idx)
         if slave_bus is None:
             slave_bus = Interface(addr_width=self.address_width,
                             data_width=self.data_width,
-                            features=features,
+                            features=slave_features,
                             granularity=self.granularity,
                             name=name+"_wb_%d_slave" % self.idx)
         self.master_bus = master_bus
@@ -99,7 +102,11 @@ class WBAsyncBridge(Elaboratable):
                             # Parameters
                             p_ADDR_WIDTH=self.address_width,
                             p_DATA_WIDTH=self.data_width,
-                            p_SELECT_WIDTH=self.granularity,
+                            # width of select is the data width
+                            # *divided* by the data granularity.
+                            # data_width=32-bit, data granularity=8-bit,
+                            # select_width ==> 32/8 ==> 4
+                            p_SELECT_WIDTH=self.data_width//self.granularity,
 
                             # Clocks/resets
                             i_wbm_clk=self.wb_mclk,
@@ -132,12 +139,6 @@ class WBAsyncBridge(Elaboratable):
                             i_wbs_rty_i=slave_rty
                             );
 
-        # Synthesize STALL signal for master port
-        comb += self.master_bus.stall.eq(self.master_bus.cyc & ~self.master_bus.ack)
-
-        # Convert incoming slave STALL signal to a format that the async bridge understands...
-        comb += slave_ack.eq(self.slave_bus.ack & ~self.slave_bus.stall)
-
         # Wire unused signals to 0
         comb += slave_err.eq(0)
         comb += slave_rty.eq(0)
@@ -147,13 +148,19 @@ class WBAsyncBridge(Elaboratable):
         return m
 
     def ports(self):
-        return [self.master_bus.adr, self.master_bus.dat_w, self.master_bus.dat_r,
-                        self.master_bus.we, self.master_bus.sel, self.master_bus.stb,
-                        self.master_bus.cyc, self.master_bus.ack, self.master_bus.err,
+        return [self.master_bus.adr, self.master_bus.dat_w,
+                        self.master_bus.dat_r,
+                        self.master_bus.we, self.master_bus.sel,
+                        self.master_bus.stb,
+                        self.master_bus.cyc, self.master_bus.ack,
+                        self.master_bus.err,
                         self.master_bus.rty,
-                        self.slave_bus.adr, self.slave_bus.dat_w, self.slave_bus.dat_r,
-                        self.slave_bus.we, self.slave_bus.sel, self.slave_bus.stb,
-                        self.slave_bus.cyc, self.slave_bus.ack, self.slave_bus.err,
+                        self.slave_bus.adr, self.slave_bus.dat_w,
+                        self.slave_bus.dat_r,
+                        self.slave_bus.we, self.slave_bus.sel,
+                        self.slave_bus.stb,
+                        self.slave_bus.cyc, self.slave_bus.ack,
+                        self.slave_bus.err,
                         self.slave_bus.rty
                        ]
 
@@ -170,4 +177,4 @@ def create_verilog(dut, ports, test_name):
 
 if __name__ == "__main__":
     wbasyncbridge = WBAsyncBridge(name="wbasyncbridge_0", address_width=30, data_width=32, granularity=8)
-    create_ilang(wbasyncbridge, wbasyncbridge.ports(), "wbasyncbridge_0")
\ No newline at end of file
+    create_ilang(wbasyncbridge, wbasyncbridge.ports(), "wbasyncbridge_0")