for *write* the counter-address on downconvert was correct

[soc.git] / src / soc / bus / wb_downconvert.py

diff --git a/src/soc/bus/wb_downconvert.py b/src/soc/bus/wb_downconvert.py
index 2b03d56bcee02b95e201d0e8fde885a34effb97c..fbf8239fe1c1ce157a8abb3e77ad0530c4058a3c 100644 (file)
--- a/src/soc/bus/wb_downconvert.py
+++ b/src/soc/bus/wb_downconvert.py
@@ -73,8 +73,7 @@ class WishboneDownConvert(Elaboratable):
                     comb += slave.cyc.eq(1)
                     comb += slave.stb.eq(1)
                     with m.If(slave.ack | skip):
-                        comb += cur_counter.eq(counter + 1) # TODO use Picker
-                        sync += counter.eq(cur_counter)
+                        sync += counter.eq(counter + 1)
                         with m.If(counter_done):
                             comb += master.ack.eq(1)
                             m.next = "IDLE"