decode predicate src/dest zeroing in SVP64RMModeDecode

[soc.git] / src / soc / consts.py

diff --git a/src/soc/consts.py b/src/soc/consts.py
index 76b16f2b4fd944adc578889aa554a8185e81ebd1..2af98d913bc903325fa7e254b717ecab9580743d 100644 (file)
--- a/src/soc/consts.py
+++ b/src/soc/consts.py
@@ -220,8 +220,8 @@ class SVP64MODEb:
     MOD2_MSB = 0
     MOD2_LSB = 1
     # when predicate not set: 0=ignore/skip 1=zero
-    SZ = 3  # for source
-    DZ = 4  # for destination
+    DZ = 3  # for destination
+    SZ = 4  # for source
     # reduce mode
     REDUCE = 2  # 0=normal predication 1=reduce mode
     SVM = 3  # subvector reduce mode 0=independent 1=horizontal