name core_stop and terminated_o synchronous to potentially help

[soc.git] / src / soc / debug / dmi.py

diff --git a/src/soc/debug/dmi.py b/src/soc/debug/dmi.py
index cda675ac89ca9dfb8a8a6dd3488907c8d1dd4bec..03bd8dc8eabcde75a191147a666ad9086b120ac5 100644 (file)
--- a/src/soc/debug/dmi.py
+++ b/src/soc/debug/dmi.py
@@ -256,6 +256,7 @@ class CoreDebug(Elaboratable):
                             continue
                         with m.If(dmi.din == 32+i):
                             sync += fast_index.eq(i)
+                            sync += fast_en.eq(1)
 
                 # Log address
                 with m.Elif(dmi.addr_i == DBGCore.LOG_ADDR):
@@ -291,10 +292,13 @@ class CoreDebug(Elaboratable):
         comb += d_fast.addr.eq(fast_index)
 
         # Core control signals generated by the debug module
-        comb += self.core_stop_o.eq((stopping & ~do_step) | self.terminate_i)
+        # Note: make stop and terminated synchronous, to help with timing
+        # however this *may* interfere with some of the DMI-based unit tests
+        # so has to be kept an eye on
+        sync += self.core_stop_o.eq((stopping & ~do_step) | self.terminate_i)
+        sync += self.terminated_o.eq(terminated | self.terminate_i)
         comb += self.core_rst_o.eq(do_reset)
         comb += self.icache_rst_o.eq(do_icreset)
-        comb += self.terminated_o.eq(terminated | self.terminate_i)
 
         # Logging RAM (none)