-from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay
-from nmigen.test.utils import FHDLTestCase
-import unittest
-from soc.decoder.isa.caller import ISACaller
-from soc.decoder.power_decoder import (create_pdecode)
-from soc.decoder.power_decoder2 import (PowerDecode2)
-from soc.simulator.program import Program
-from soc.decoder.isa.caller import ISACaller, inject
-from soc.decoder.selectable_int import SelectableInt
-from soc.decoder.orderedset import OrderedSet
-from soc.decoder.isa.all import ISA
+# moved to openpower-isa
+# https://git.libre-soc.org/?p=openpower-isa.git;a=summary
+# wildcard imports here ONLY to support migration
-
-class Register:
- def __init__(self, num):
- self.num = num
-
-
-class DecoderTestCase(FHDLTestCase):
-
- def run_tst(self, generator, initial_regs):
- m = Module()
- comb = m.d.comb
- instruction = Signal(32)
-
- pdecode = create_pdecode()
- simulator = ISA(pdecode, initial_regs)
-
- m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
- comb += pdecode2.dec.raw_opcode_in.eq(instruction)
- sim = Simulator(m)
- gen = generator.generate_instructions()
-
- def process():
- instructions = list(zip(gen, generator.assembly.splitlines()))
-
- index = simulator.pc.CIA.value//4
- while index < len(instructions):
- ins, code = instructions[index]
-
- print("0x{:X}".format(ins & 0xffffffff))
- print(code)
-
- # ask the decoder to decode this binary data (endian'd)
- yield pdecode2.dec.bigendian.eq(0) # little / big?
- yield instruction.eq(ins) # raw binary instr.
- yield Delay(1e-6)
- opname = code.split(' ')[0]
- yield from simulator.call(opname)
- index = simulator.pc.CIA.value//4
-
- sim.add_process(process)
- with sim.write_vcd("simulator.vcd", "simulator.gtkw",
- traces=[]):
- sim.run()
- return simulator
-
- def test_add(self):
- lst = ["add 1, 3, 2"]
- initial_regs = [0] * 32
- initial_regs[3] = 0x1234
- initial_regs[2] = 0x4321
- with Program(lst) as program:
- sim = self.run_tst_program(program, initial_regs)
- self.assertEqual(sim.gpr(1), SelectableInt(0x5555, 64))
-
- def test_addi(self):
- lst = ["addi 3, 0, 0x1234",
- "addi 2, 0, 0x4321",
- "add 1, 3, 2"]
- with Program(lst) as program:
- sim = self.run_tst_program(program)
- print(sim.gpr(1))
- self.assertEqual(sim.gpr(1), SelectableInt(0x5555, 64))
-
- def test_load_store(self):
- lst = ["addi 1, 0, 0x0010",
- "addi 2, 0, 0x1234",
- "stw 2, 0(1)",
- "lwz 3, 0(1)"]
- with Program(lst) as program:
- sim = self.run_tst_program(program)
- print(sim.gpr(1))
- self.assertEqual(sim.gpr(3), SelectableInt(0x1234, 64))
-
- def test_addpcis(self):
- lst = ["addpcis 1, 0x1",
- "addpcis 2, 0x1",
- "addpcis 3, 0x1"]
- with Program(lst) as program:
- sim = self.run_tst_program(program)
- self.assertEqual(sim.gpr(1), SelectableInt(0x10004, 64))
- self.assertEqual(sim.gpr(2), SelectableInt(0x10008, 64))
- self.assertEqual(sim.gpr(3), SelectableInt(0x1000c, 64))
-
- def test_branch(self):
- lst = ["ba 0xc", # branch to line 4
- "addi 1, 0, 0x1234", # Should never execute
- "ba 0x1000", # exit the program
- "addi 2, 0, 0x1234", # line 4
- "ba 0x8"] # branch to line 3
- with Program(lst) as program:
- sim = self.run_tst_program(program)
- self.assertEqual(sim.pc.CIA, SelectableInt(0x1000, 64))
- self.assertEqual(sim.gpr(1), SelectableInt(0x0, 64))
- self.assertEqual(sim.gpr(2), SelectableInt(0x1234, 64))
-
- @unittest.skip("broken") # FIXME
- def test_mtcrf(self):
- for i in range(4):
- # 0x7654 gives expected (3+4) (2+4) (1+4) (0+4) for i=3,2,1,0
- lst = ["addi %d, 0, 0x7654" % (i+1),
- "mtcrf %d, %d" % (1 << i, i+1),
- ]
- with Program(lst) as program:
- sim = self.run_tst_program(program)
- print("cr", sim.cr)
- expected = (i+4)
- # check CR itself
- self.assertEqual(sim.cr, SelectableInt(expected << (i*4), 32))
- # check CR[0]/1/2/3 as well
- print("cr%d", sim.crl[i])
- self.assertTrue(SelectableInt(expected, 4) == sim.crl[i])
-
- def run_tst_program(self, prog, initial_regs=[0] * 32):
- simulator = self.run_tst(prog, initial_regs)
- simulator.gpr.dump()
- return simulator
-
-
-if __name__ == "__main__":
- unittest.main()
+from openpower.decoder.isa.test_caller import *
projects / soc.git / blobdiff