read predicate mask from correct point in SVP64Asm

[soc.git] / src / soc / decoder / isa / test_caller_svp64_predication.py

diff --git a/src/soc/decoder/isa/test_caller_svp64_predication.py b/src/soc/decoder/isa/test_caller_svp64_predication.py
index 837c42d89a5da871179b5ad1b92790f77dcc7371..46486c2ecf9865966741f9e72fc449def16a624f 100644 (file)
--- a/src/soc/decoder/isa/test_caller_svp64_predication.py
+++ b/src/soc/decoder/isa/test_caller_svp64_predication.py
@@ -64,7 +64,7 @@ class DecoderTestCase(FHDLTestCase):
         #                              |
         #   dest r3=0b10             N Y
 
-        isa = SVP64Asm(['sv.extsb/sm=~r3/m=r3 5.v, 9.v'
+        isa = SVP64Asm(['sv.extsb/sm=~r3/dm=r3 5.v, 9.v'
                        ])
         lst = list(isa)
         print ("listing", lst)
@@ -90,7 +90,7 @@ class DecoderTestCase(FHDLTestCase):
 
     def test_sv_extsw_intpred_dz(self):
         # extsb, integer twin-pred mask: dest is r3 (0b01), zeroing on dest
-        isa = SVP64Asm(['sv.extsb/m=r3/dz 5.v, 9.v'
+        isa = SVP64Asm(['sv.extsb/dm=r3/dz 5.v, 9.v'
                        ])
         lst = list(isa)
         print ("listing", lst)
@@ -120,7 +120,7 @@ class DecoderTestCase(FHDLTestCase):
         # adds, integer predicated mask r3=0b10
         #       1 = 5 + 9   => not to be touched (skipped)
         #       2 = 6 + 10  => 0x3334 = 0x2223+0x1111
-        isa = SVP64Asm(['sv.add/m=r3 1.v, 5.v, 9.v'
+        isa = SVP64Asm(['sv.add/dm=r3 1.v, 5.v, 9.v'
                        ])
         lst = list(isa)
         print ("listing", lst)
@@ -151,7 +151,7 @@ class DecoderTestCase(FHDLTestCase):
         # adds, CR predicated mask CR4.eq = 1, CR5.eq = 0, invert (ne)
         #       1 = 5 + 9   => not to be touched (skipped)
         #       2 = 6 + 10  => 0x3334 = 0x2223+0x1111
-        isa = SVP64Asm(['sv.add/m=ne 1.v, 5.v, 9.v'
+        isa = SVP64Asm(['sv.add/dm=ne 1.v, 5.v, 9.v'
                        ])
         lst = list(isa)
         print ("listing", lst)