from nmigen.cli import rtlil
from soc.decoder.power_enums import (Function, Form, MicrOp,
In1Sel, In2Sel, In3Sel, OutSel,
- SVEtype, SVPtype, # Simple-V
+ SVEXTRA, SVEtype, SVPtype, # Simple-V
RC, LdstLen, LDSTMode, CryIn,
single_bit_flags, CRInSel,
CROutSel, get_signal_name,
'out_sel': OutSel,
'cr_in': CRInSel,
'cr_out': CROutSel,
+ 'sv_in1': SVEXTRA,
+ 'sv_in2': SVEXTRA,
+ 'sv_in3': SVEXTRA,
+ 'sv_out': SVEXTRA,
+ 'sv_cr_in': SVEXTRA,
+ 'sv_cr_out': SVEXTRA,
'ldst_len': LdstLen,
'upd': LDSTMode,
'rc_sel': RC,
'in2_sel': 'in2',
'in3_sel': 'in3',
'out_sel': 'out',
+ 'sv_in1': 'sv_in1',
+ 'sv_in2': 'sv_in2',
+ 'sv_in3': 'sv_in3',
+ 'sv_out': 'sv_out',
+ 'sv_cr_in': 'sv_cr_in',
+ 'sv_cr_out': 'sv_cr_out',
+ 'SV_Etype': 'SV_Etype',
+ 'SV_Ptype': 'SV_Ptype',
'cr_in': 'CR in',
'cr_out': 'CR out',
'ldst_len': 'ldst len',
return "%s_%s" % (pname, field)
+class PatternOpcode(str):
+ pass
+
+
+def parse_opcode(opcode, opint=True):
+ assert opint
+ if isinstance(opcode, (int, PatternOpcode)):
+ return opcode
+ assert isinstance(opcode, str)
+ if len(opcode) > 4 or '-' in opcode:
+ # all binary numbers must start with 0b
+ assert opcode.startswith('0b')
+ if '-' not in opcode:
+ opcode = int(opcode, 0)
+ else:
+ opcode = PatternOpcode(opcode[2:])
+ return opcode
+
+
class PowerOp:
"""PowerOp - a dynamic class that stores (subsets of) CSV rows of data
about a PowerISA instruction. this is a "micro-code" expanded format
if field not in power_op_csvmap:
continue
csvname = power_op_csvmap[field]
+ print(field, ptype, csvname, row)
val = row[csvname]
if csvname == 'upd' and isinstance(val, int): # LDSTMode different
val = ptype(val)
mask = self.suffix_mask(d)
print("mask", hex(mask))
for row in d.opcodes:
- opcode = row['opcode']
- if d.opint and '-' not in opcode:
- opcode = int(opcode, 0)
+ opcode = parse_opcode(row['opcode'], d.opint)
key = opcode & mask
opcode = opcode >> d.suffix
if key not in divided:
bitsel = (d.suffix+d.bitsel[0], d.bitsel[1])
sd = Subdecoder(pattern=None, opcodes=row,
bitsel=bitsel, suffix=None,
- opint=False, subdecoders=[])
+ opint=True, subdecoders=[])
mname = get_pname("dec_sub%d" % key, self.pname)
subdecoder = PowerDecoder(width=32, dec=sd,
name=mname,
case_does_something = True
eq += seqs
for row in d.opcodes:
- opcode = row['opcode']
- if d.opint and '-' not in opcode:
- opcode = int(opcode, 0)
+ opcode = parse_opcode(row['opcode'], d.opint)
if not row['unit']:
continue
if self.row_subsetfn:
def elaborate(self, platform):
m = PowerDecoder.elaborate(self, platform)
comb = m.d.comb
+ # sigh duplicated in SVP64PowerDecoder
# raw opcode in assumed to be in LE order: byte-reverse it to get BE
raw_le = self.raw_opcode_in
l = []
opint=True, bitsel=(0, 2), suffix=None, subdecoders=[]),
Subdecoder(pattern=62, opcodes=get_csv("minor_62.csv"),
opint=True, bitsel=(0, 2), suffix=None, subdecoders=[]),
+ Subdecoder(pattern=22, opcodes=get_csv("minor_22.csv"),
+ opint=True, bitsel=(1, 5), suffix=None, subdecoders=[]),
]
# top level: extra merged with major
dec.append(Subdecoder(pattern=None, opint=True, opcodes=opcodes,
bitsel=(26, 32), suffix=None, subdecoders=pminor))
opcodes = get_csv("extra.csv")
- dec.append(Subdecoder(pattern=None, opint=False, opcodes=opcodes,
+ dec.append(Subdecoder(pattern=None, opint=True, opcodes=opcodes,
bitsel=(0, 32), suffix=None, subdecoders=[]))
return TopPowerDecoder(32, dec, name=name, col_subset=col_subset,