add XER to fastregs and "construct" it in mfspr/mtspr

[soc.git] / src / soc / decoder / power_decoder2.py

diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index 1bdcd3ffc83a791e6b13905551e86f5209f19635..4405cf2c2631a33a934f70d57964859b71941f93 100644 (file)
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -147,6 +147,8 @@ class DecodeA(Elaboratable):
                         comb += self.fast_out.data.eq(FastRegs.SRR1)
                         comb += self.fast_out.ok.eq(1)
                     with m.Case(SPR.XER.value):
+                        comb += self.fast_out.data.eq(FastRegs.XER)
+                        comb += self.fast_out.ok.eq(1)
                         pass  # do nothing
                     # : map to internal SPR numbers
                     # XXX TODO: dec and tb not to go through mapping.
@@ -328,6 +330,8 @@ class DecodeOut(Elaboratable):
                             comb += self.fast_out.data.eq(FastRegs.SRR1)
                             comb += self.fast_out.ok.eq(1)
                         with m.Case(SPR.XER.value):
+                            comb += self.fast_out.data.eq(FastRegs.XER)
+                            comb += self.fast_out.ok.eq(1)
                             pass  # do nothing
                         # : map to internal SPR numbers
                         # XXX TODO: dec and tb not to go through mapping.