simplify instr_is_priv

[soc.git] / src / soc / decoder / power_decoder2.py

diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index 9f46e3f032326922de9d2568797ca1dc73e18500..5abf8314d3b2a803a01d6dc40641a00e3d1232b8 100644 (file)
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -36,11 +36,9 @@ def instr_is_priv(m, op, insn):
     comb = m.d.comb
     is_priv_insn = Signal(reset_less=True)
     with m.Switch(op):
-        with m.Case(MicrOp.OP_ATTN)  : comb += is_priv_insn.eq(1)
-        with m.Case(MicrOp.OP_MFMSR) : comb += is_priv_insn.eq(1)
-        with m.Case(MicrOp.OP_MTMSRD): comb += is_priv_insn.eq(1)
-        with m.Case(MicrOp.OP_MTMSR): comb += is_priv_insn.eq(1)
-        with m.Case(MicrOp.OP_RFID)  : comb += is_priv_insn.eq(1)
+        with m.Case(MicrOp.OP_ATTN, MicrOp.OP_MFMSR, MicrOp.OP_MTMSRD,
+                    MicrOp.OP_MTMSR, MicrOp.OP_RFID):
+            comb += is_priv_insn.eq(1)
         # XXX TODO
         #with m.Case(MicrOp.OP_TLBIE) : comb += is_priv_insn.eq(1)
         with m.Case(MicrOp.OP_MFSPR, MicrOp.OP_MTSPR):