allow ALU / Logical ops to select RS as 1st operand

[soc.git] / src / soc / decoder / power_decoder2.py

diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index 81ab714390133691d7401240998e54be36a99e6b..d12566d0a59125ef1e2c19c68b276a3ae63e3714 100644 (file)
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -49,6 +49,11 @@ class DecodeA(Elaboratable):
                   (self.reg_out.data == Const(0, 5))):
             comb += self.immz_out.eq(1)
 
+        # some Logic/ALU ops have RS as the 3rd arg, but no "RA".
+        with m.If(self.sel_in == In1Sel.RS):
+            comb += self.reg_out.data.eq(self.dec.RS)
+            comb += self.reg_out.ok.eq(1)
+
         # decode SPR1 based on instruction type
         op = self.dec.op
         # BC or BCREG: potential implicit register (CTR)