whoops swap regs and form

[soc.git] / src / soc / decoder / pseudo / pywriter.py

diff --git a/src/soc/decoder/pseudo/pywriter.py b/src/soc/decoder/pseudo/pywriter.py
index 0dc41784ccde4a6a9a8a79c1832b48e555a6f718..c33f944cad45348a16307a3ce863aa5b6fffa513 100644 (file)
--- a/src/soc/decoder/pseudo/pywriter.py
+++ b/src/soc/decoder/pseudo/pywriter.py
@@ -1,6 +1,7 @@
 # python code-writer for OpenPOWER ISA pseudo-code parsing
 
 import os
+import sys
 from soc.decoder.pseudo.pagereader import ISA
 from soc.decoder.power_pseudo import convert_to_python
 from soc.decoder.orderedset import OrderedSet
@@ -15,21 +16,28 @@ def get_isasrc_dir():
 header = """\
 # auto-generated by pywriter.py, do not edit or commit
 
-from soc.decoder.isa.caller import ISACaller, inject
+from soc.decoder.isa.caller import inject
 from soc.decoder.helpers import (EXTS, EXTS64, EXTZ64, ROTL64, ROTL32, MASK,)
 from soc.decoder.selectable_int import SelectableInt
 from soc.decoder.selectable_int import selectconcat as concat
 from soc.decoder.orderedset import OrderedSet
 
-class %s(ISACaller):
+class %s:
 
 """
 
+iinfo_template = """(%s, %s,
+                %s, %s,
+                %s, '%s',
+                %s)"""
+
 class PyISAWriter(ISA):
     def __init__(self):
         ISA.__init__(self)
+        self.pages_written = []
 
     def write_pysource(self, pagename):
+        self.pages_written.append(pagename)
         instrs = isa.page[pagename]
         isadir = get_isasrc_dir()
         fname = os.path.join(isadir, "%s.py" % pagename)
@@ -42,7 +50,7 @@ class PyISAWriter(ISA):
                 print (fname, d.opcode)
                 pcode = '\n'.join(d.pcode) + '\n'
                 print (pcode)
-                pycode, rused = convert_to_python(pcode)
+                pycode, rused = convert_to_python(pcode, d.form)
                 # create list of arguments to call
                 regs = list(rused['read_regs']) + list(rused['uninit_regs'])
                 args = ', '.join(create_args(regs, 'self'))
@@ -62,23 +70,42 @@ class PyISAWriter(ISA):
                 else:
                     f.write("\n")
                 # accumulate the instruction info
-                iinfo = "(%s, %s,\n                %s, %s)" % \
-                            (op_fname, rused['read_regs'],
-                            rused['uninit_regs'], rused['write_regs'])
-                iinf += "    instrs['%s'] = %s\n" % (page, iinfo)
+                ops = repr(rused['op_fields'])
+                iinfo = iinfo_template % (op_fname, rused['read_regs'],
+                                rused['uninit_regs'], rused['write_regs'],
+                                ops, d.regs, d.form)
+                iinf += "    %s_instrs['%s'] = %s\n" % (pagename, page, iinfo)
             # write out initialisation of info, for ISACaller to use
-            f.write("    instrs = {}\n")
+            f.write("    %s_instrs = {}\n" % pagename)
             f.write(iinf)
 
+    def write_isa_class(self):
+        isadir = get_isasrc_dir()
+        fname = os.path.join(isadir, "all.py")
+
+        with open(fname, "w") as f:
+            f.write('from soc.decoder.isa.caller import ISACaller\n')
+            for page in self.pages_written:
+                f.write('from soc.decoder.isa.%s import %s\n' % (page, page))
+            f.write('\n')
+
+            classes = ', '.join(['ISACaller'] + self.pages_written)
+            f.write('class ISA(%s):\n' % classes)
+            f.write('    def __init__(self, dec, regs):\n')
+            f.write('        super().__init__(dec, regs)\n')
+            f.write('        self.instrs = {\n')
+            for page in self.pages_written:
+                f.write('            **self.%s_instrs,\n' % page)
+            f.write('        }\n')
+
+
 if __name__ == '__main__':
     isa = PyISAWriter()
-    isa.write_pysource('fixedshift')
-    exit(0)
-    isa.write_pysource('condition')
-    isa.write_pysource('fixedtrap')
-    isa.write_pysource('branch')
-    isa.write_pysource('fixedlogical')
-    isa.write_pysource('fixedstore')
-    isa.write_pysource('fixedload')
-    isa.write_pysource('comparefixed')
-    isa.write_pysource('fixedarith')
+    if len(sys.argv) == 1: # quick way to do it
+        print (dir(isa))
+        sources = isa.page.keys()
+    else:
+        sources = sys.argv[1:]
+    for source in sources:
+        isa.write_pysource(source)
+    isa.write_isa_class()