Demonstrates creating stylish GTKWave "save" files from python

[soc.git] / src / soc / experiment / alu_fsm.py

diff --git a/src/soc/experiment/alu_fsm.py b/src/soc/experiment/alu_fsm.py
index 606b4790566d4c188b0f4d0bb60f452e1e9a5a94..3a3d9db111af3d9152d21017b96048746662562f 100644 (file)
--- a/src/soc/experiment/alu_fsm.py
+++ b/src/soc/experiment/alu_fsm.py
@@ -17,7 +17,11 @@ The basic rules are:
 """
 
 from nmigen import Elaboratable, Signal, Module, Cat
-from nmigen.back.pysim import Simulator
+cxxsim = False
+if cxxsim:
+    from nmigen.sim.cxxsim import Simulator, Settle
+else:
+    from nmigen.back.pysim import Simulator, Settle
 from nmigen.cli import rtlil
 from math import log2
 from nmutil.iocontrol import PrevControl, NextControl
@@ -25,10 +29,12 @@ from nmutil.iocontrol import PrevControl, NextControl
 from soc.fu.base_input_record import CompOpSubsetBase
 from soc.decoder.power_enums import (MicrOp, Function)
 
+from vcd.gtkw import GTKWSave, GTKWColor
+
 
 class CompFSMOpSubset(CompOpSubsetBase):
     def __init__(self, name=None):
-        layout = (('dir', 1),
+        layout = (('sdir', 1),
                   )
 
         super().__init__(layout, name=name)
@@ -49,7 +55,9 @@ class Shifter(Elaboratable):
     *                 On POWER, range is 0 to 63 for 32-bit,
     *                 and 0 to 127 for 64-bit.
     *                 Other values wrap around.
-    * p.data_i.sdir:   shift direction (0 = left, 1 = right)
+
+    Operation type
+    * op.sdir:       shift direction (0 = left, 1 = right)
 
     Next port data:
     * n.data_o.data: shifted value
@@ -58,7 +66,6 @@ class Shifter(Elaboratable):
         def __init__(self, width):
             self.data = Signal(width, name="p_data_i")
             self.shift = Signal(width, name="p_shift_i")
-            self.sdir = Signal(name="p_sdir_i")
             self.ctx = Dummy() # comply with CompALU API
 
         def _get_data(self):
@@ -79,7 +86,7 @@ class Shifter(Elaboratable):
         self.n.data_o = Shifter.NextData(width)
 
         # more pieces to make this example class comply with the CompALU API
-        self.op = CompFSMOpSubset()
+        self.op = CompFSMOpSubset(name="op")
         self.p.data_i.ctx.op = self.op
         self.i = self.p.data_i._get_data()
         self.out = self.n.data_o._get_data()
@@ -157,7 +164,7 @@ class Shifter(Elaboratable):
                     next_count.eq(self.p.data_i.shift),
                 ]
                 # capture the direction bit as well
-                m.d.sync += direction.eq(self.p.data_i.sdir)
+                m.d.sync += direction.eq(self.op.sdir)
                 with m.If(self.p.valid_i):
                     # Leave IDLE when data arrives
                     with m.If(next_count == 0):
@@ -185,9 +192,9 @@ class Shifter(Elaboratable):
         return m
 
     def __iter__(self):
+        yield self.op.sdir
         yield self.p.data_i.data
         yield self.p.data_i.shift
-        yield self.p.data_i.sdir
         yield self.p.valid_i
         yield self.p.ready_o
         yield self.n.ready_i
@@ -198,6 +205,43 @@ class Shifter(Elaboratable):
         return list(self)
 
 
+# Write a formatted GTKWave "save" file
+def write_gtkw(base_name, top_dut_name, loc):
+    # hierarchy path, to prepend to signal names
+    dut = top_dut_name + "."
+    # color styles
+    style_input = GTKWColor.orange
+    style_output = GTKWColor.yellow
+    with open(base_name + ".gtkw", "wt") as gtkw_file:
+        gtkw = GTKWSave(gtkw_file)
+        gtkw.comment("Auto-generated by " + loc)
+        gtkw.dumpfile(base_name + ".vcd")
+        # set a reasonable zoom level
+        # also, move the marker to an interesting place
+        gtkw.zoom_markers(-22.9, 10500000)
+        gtkw.trace(dut + "clk")
+        # place a comment in the signal names panel
+        gtkw.blank("Shifter Demonstration")
+        with gtkw.group("prev port"):
+            gtkw.trace(dut + "op__sdir", color=style_input)
+            # demonstrates using decimal base (default is hex)
+            gtkw.trace(dut + "p_data_i[7:0]", color=style_input,
+                       datafmt='dec')
+            gtkw.trace(dut + "p_shift_i[7:0]", color=style_input,
+                       datafmt='dec')
+            gtkw.trace(dut + "p_valid_i", color=style_input)
+            gtkw.trace(dut + "p_ready_o", color=style_output)
+        with gtkw.group("internal"):
+            gtkw.trace(dut + "fsm_state")
+            gtkw.trace(dut + "count[3:0]")
+            gtkw.trace(dut + "shift_reg[7:0]", datafmt='dec')
+        with gtkw.group("next port"):
+            gtkw.trace(dut + "n_data_o[7:0]", color=style_output,
+                       datafmt='dec')
+            gtkw.trace(dut + "n_valid_o", color=style_output)
+            gtkw.trace(dut + "n_ready_i", color=style_input)
+
+
 def test_shifter():
     m = Module()
     m.submodules.shf = dut = Shifter(8)
@@ -209,6 +253,10 @@ def test_shifter():
     il = rtlil.convert(dut, ports=dut.ports())
     with open("test_shifter.il", "w") as f:
         f.write(il)
+
+    # Write the GTKWave project file
+    write_gtkw("test_shifter", "top.shf", __file__)
+
     sim = Simulator(m)
     sim.add_clock(1e-6)
 
@@ -216,7 +264,7 @@ def test_shifter():
         # present input data and assert valid_i
         yield dut.p.data_i.data.eq(data)
         yield dut.p.data_i.shift.eq(shift)
-        yield dut.p.data_i.sdir.eq(direction)
+        yield dut.op.sdir.eq(direction)
         yield dut.p.valid_i.eq(1)
         yield
         # wait for p.ready_o to be asserted
@@ -226,7 +274,7 @@ def test_shifter():
         yield dut.p.valid_i.eq(0)
         yield dut.p.data_i.data.eq(0)
         yield dut.p.data_i.shift.eq(0)
-        yield dut.p.data_i.sdir.eq(0)
+        yield dut.op.sdir.eq(0)
 
     def receive(expected):
         # signal readiness to receive data
@@ -264,8 +312,6 @@ def test_shifter():
     sim.add_sync_process(consumer)
     sim_writer = sim.write_vcd(
         "test_shifter.vcd",
-        "test_shifter.gtkw",
-        traces=dut.ports()
     )
     with sim_writer:
         sim.run()