Demonstrates creating stylish GTKWave "save" files from python
[soc.git] / src / soc / experiment / alu_fsm.py
index b3ab5b175a1edd9128d3cbd9db29c1e634e7a1ab..3a3d9db111af3d9152d21017b96048746662562f 100644 (file)
@@ -29,6 +29,8 @@ from nmutil.iocontrol import PrevControl, NextControl
 from soc.fu.base_input_record import CompOpSubsetBase
 from soc.decoder.power_enums import (MicrOp, Function)
 
+from vcd.gtkw import GTKWSave, GTKWColor
+
 
 class CompFSMOpSubset(CompOpSubsetBase):
     def __init__(self, name=None):
@@ -53,7 +55,9 @@ class Shifter(Elaboratable):
     *                 On POWER, range is 0 to 63 for 32-bit,
     *                 and 0 to 127 for 64-bit.
     *                 Other values wrap around.
-    * p.data_i.sdir:   shift direction (0 = left, 1 = right)
+
+    Operation type
+    * op.sdir:       shift direction (0 = left, 1 = right)
 
     Next port data:
     * n.data_o.data: shifted value
@@ -82,7 +86,7 @@ class Shifter(Elaboratable):
         self.n.data_o = Shifter.NextData(width)
 
         # more pieces to make this example class comply with the CompALU API
-        self.op = CompFSMOpSubset()
+        self.op = CompFSMOpSubset(name="op")
         self.p.data_i.ctx.op = self.op
         self.i = self.p.data_i._get_data()
         self.out = self.n.data_o._get_data()
@@ -201,6 +205,43 @@ class Shifter(Elaboratable):
         return list(self)
 
 
+# Write a formatted GTKWave "save" file
+def write_gtkw(base_name, top_dut_name, loc):
+    # hierarchy path, to prepend to signal names
+    dut = top_dut_name + "."
+    # color styles
+    style_input = GTKWColor.orange
+    style_output = GTKWColor.yellow
+    with open(base_name + ".gtkw", "wt") as gtkw_file:
+        gtkw = GTKWSave(gtkw_file)
+        gtkw.comment("Auto-generated by " + loc)
+        gtkw.dumpfile(base_name + ".vcd")
+        # set a reasonable zoom level
+        # also, move the marker to an interesting place
+        gtkw.zoom_markers(-22.9, 10500000)
+        gtkw.trace(dut + "clk")
+        # place a comment in the signal names panel
+        gtkw.blank("Shifter Demonstration")
+        with gtkw.group("prev port"):
+            gtkw.trace(dut + "op__sdir", color=style_input)
+            # demonstrates using decimal base (default is hex)
+            gtkw.trace(dut + "p_data_i[7:0]", color=style_input,
+                       datafmt='dec')
+            gtkw.trace(dut + "p_shift_i[7:0]", color=style_input,
+                       datafmt='dec')
+            gtkw.trace(dut + "p_valid_i", color=style_input)
+            gtkw.trace(dut + "p_ready_o", color=style_output)
+        with gtkw.group("internal"):
+            gtkw.trace(dut + "fsm_state")
+            gtkw.trace(dut + "count[3:0]")
+            gtkw.trace(dut + "shift_reg[7:0]", datafmt='dec')
+        with gtkw.group("next port"):
+            gtkw.trace(dut + "n_data_o[7:0]", color=style_output,
+                       datafmt='dec')
+            gtkw.trace(dut + "n_valid_o", color=style_output)
+            gtkw.trace(dut + "n_ready_i", color=style_input)
+
+
 def test_shifter():
     m = Module()
     m.submodules.shf = dut = Shifter(8)
@@ -212,6 +253,10 @@ def test_shifter():
     il = rtlil.convert(dut, ports=dut.ports())
     with open("test_shifter.il", "w") as f:
         f.write(il)
+
+    # Write the GTKWave project file
+    write_gtkw("test_shifter", "top.shf", __file__)
+
     sim = Simulator(m)
     sim.add_clock(1e-6)
 
@@ -240,9 +285,6 @@ def test_shifter():
             yield
         # read result
         result = yield dut.n.data_o.data
-
-        # must leave ready_i valid for 1 cycle, ready_i to register for 1 cycle
-        yield
         # negate n.ready_i
         yield dut.n.ready_i.eq(0)
         # check result