Add CR to the output data port

[soc.git] / src / soc / experiment / alu_hier.py

diff --git a/src/soc/experiment/alu_hier.py b/src/soc/experiment/alu_hier.py
index 83354d44f16cb8fc105f98e6e20c57d8c302986d..a780dd86357e4c5cb1fc75148d38911b509bf380 100644 (file)
--- a/src/soc/experiment/alu_hier.py
+++ b/src/soc/experiment/alu_hier.py
@@ -208,6 +208,7 @@ class ALU(Elaboratable):
         self.p.data_i.a = self.a
         self.p.data_i.b = self.b
         self.n.data_o.o = self.o
+        self.n.data_o.cr = self.cr
 
     def elaborate(self, platform):
         m = Module()