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[soc.git] / src / soc / experiment / alu_hier.py

diff --git a/src/soc/experiment/alu_hier.py b/src/soc/experiment/alu_hier.py
index 9659059c79edd74cb79bde61a36149b3361c6d26..f1606198bd0fe5e4f7a9496d43fb7a3c4c8243a8 100644 (file)
--- a/src/soc/experiment/alu_hier.py
+++ b/src/soc/experiment/alu_hier.py
@@ -1,3 +1,14 @@
+"""*Experimental* ALU: based on nmigen alu_hier.py, includes branch-compare ALU
+
+This ALU is *deliberately* designed to add in (unnecessary) delays into
+different operations so as to be able to test the 6600-style matrices
+and the CompUnits.  Countdown timers wait for (defined) periods before
+indicating that the output is valid
+
+A "real" integer ALU would place the answers onto the output bus after
+only one cycle (sync)
+"""
+
 from nmigen import Elaboratable, Signal, Module, Const, Mux
 from nmigen.cli import main
 from nmigen.cli import verilog, rtlil