Reset src_l latch on issue_i

[soc.git] / src / soc / experiment / compalu_multi.py

diff --git a/src/soc/experiment/compalu_multi.py b/src/soc/experiment/compalu_multi.py
index 1c521c4b0bf8fdc1e9a7a5b86a6dc61b51c8a66d..7eef2047bdab661879f67dba538e3f35afd02f3d 100644 (file)
--- a/src/soc/experiment/compalu_multi.py
+++ b/src/soc/experiment/compalu_multi.py
@@ -198,7 +198,7 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable):
         # ALU only proceeds when all src are ready.  rd_rel_o is delayed
         # so combine it with go_rd_i.  if all bits are set we're good
         all_rd = Signal(reset_less=True)
-        m.d.comb += all_rd.eq(self.busy_o & rok_l.q & # XXX LOOP
+        m.d.comb += all_rd.eq(self.busy_o & # rok_l.q & # XXX LOOP
                               (((~self.rd.rel_o) | self.rd.go_i).all()))
 
         # generate read-done pulse
@@ -241,7 +241,7 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable):
         m.d.comb += reset.eq(req_done | self.go_die_i)
         m.d.comb += rst_r.eq(self.issue_i | self.go_die_i)
         m.d.comb += reset_w.eq(self.wr.go_i | Repl(self.go_die_i, self.n_dst))
-        m.d.comb += reset_r.eq(self.rd.go_i | Repl(self.go_die_i, self.n_src))
+        m.d.comb += reset_r.eq(self.rd.go_i | Repl(rst_r, self.n_src))
 
         # read-done,wr-proceed latch
         rw_domain += rok_l.s.eq(self.issue_i)  # set up when issue starts
@@ -258,7 +258,7 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable):
         # src operand latch (not using go_wr_i) ANDed with rdmask
         rdmaskn = Signal(self.n_src)
         latchregister(m, self.rdmaskn, rdmaskn, self.issue_i, name="rdmask_l")
-        m.d.comb += src_l.s.eq(Repl(self.issue_i, self.n_src) & ~rdmaskn)
+        m.d.sync += src_l.s.eq(Repl(self.issue_i, self.n_src) & ~rdmaskn)
         m.d.sync += src_l.r.eq(reset_r)
 
         # dest operand latch (not using issue_i)
@@ -355,7 +355,7 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable):
         m.submodules.alu_l = alu_l = SRLatch(False, name="alu")
         m.d.comb += self.alu.n.i_ready.eq(alu_l.q)
         m.d.sync += alu_l.r.eq(self.alu.n.o_valid & alu_l.q)
-        m.d.comb += alu_l.s.eq(all_rd_pulse)
+        m.d.comb += alu_l.s.eq(all_rd_pulse) # XXX LOOP
 
         # -----
         # outputs