sort out core write latching: gate by busy, and use CompUnit dest output

[soc.git] / src / soc / experiment / compalu_multi.py

diff --git a/src/soc/experiment/compalu_multi.py b/src/soc/experiment/compalu_multi.py
index d1a4a325d348d3742a9311e782fa906bb283e2fe..bfe06c592ed2f8a6f1d0492b3eb9b434073b2a45 100644 (file)
--- a/src/soc/experiment/compalu_multi.py
+++ b/src/soc/experiment/compalu_multi.py
@@ -346,11 +346,14 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable):
 
         # output the data from the latch on go_write
         for i in range(self.n_dst):
-            with m.If(self.wr.go[i]):
+            with m.If(self.wr.go[i] & self.busy_o):
                 m.d.comb += self.dest[i].eq(drl[i])
 
         return m
 
+    def get_fu_out(self, i):
+        return self.dest[i]
+
     def __iter__(self):
         yield self.rd.go
         yield self.wr.go