bit of a big reorg of data structures

[soc.git] / src / soc / experiment / compalu_multi.py

diff --git a/src/soc/experiment/compalu_multi.py b/src/soc/experiment/compalu_multi.py
index 79d4ccd1698fada3cb4554b32cc4575c72777728..d7e32f28c556e76aff9be146ce280eba9745bb09 100644 (file)
--- a/src/soc/experiment/compalu_multi.py
+++ b/src/soc/experiment/compalu_multi.py
@@ -308,8 +308,8 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable):
         if hasattr(op, "imm_data"):
             # select immediate if opcode says so. however also change the latch
             # to trigger *from* the opcode latch instead.
-            op_is_imm = op.imm_data.imm_ok
-            imm = op.imm_data.imm
+            op_is_imm = op.imm_data.ok
+            imm = op.imm_data.data
             self._mux_op(m, sl, op_is_imm, imm, 1)
 
         # create a latch/register for src1/src2 (even if it is a copy of imm)