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[soc.git] / src / soc / experiment / compldst.py

diff --git a/src/soc/experiment/compldst.py b/src/soc/experiment/compldst.py
index 489a50112918a2bc28053d89ddc5a7ff9113474a..206f44876b00b6c1d94716e624a03e81208120d4 100644 (file)
--- a/src/soc/experiment/compldst.py
+++ b/src/soc/experiment/compldst.py
@@ -117,6 +117,7 @@ class LDSTCompUnit(Elaboratable):
         self.adr_rel_o = Signal(reset_less=True) # request address (from mem)
         self.sto_rel_o = Signal(reset_less=True) # request store (to mem)
         self.req_rel_o = Signal(reset_less=True) # request write (result)
+        self.done_o = Signal(reset_less=True) # final release signal
         self.data_o = Signal(rwid, reset_less=True) # Dest out (LD or ALU)
         self.addr_o = Signal(rwid, reset_less=True) # Address out (LD or ST)
 
@@ -145,7 +146,7 @@ class LDSTCompUnit(Elaboratable):
         reset_a = Signal(reset_less=True)
         reset_s = Signal(reset_less=True)
         reset_r = Signal(reset_less=True)
-        comb += reset_b.eq(self.go_st_i | self.go_wr_i | self.go_die_i)
+        comb += reset_b.eq(self.go_st_i|self.go_wr_i|self.go_ad_i|self.go_die_i)
         comb += reset_w.eq(self.go_wr_i | self.go_die_i)
         comb += reset_s.eq(self.go_st_i | self.go_die_i)
         comb += reset_r.eq(self.go_rd_i | self.go_die_i)
@@ -187,11 +188,11 @@ class LDSTCompUnit(Elaboratable):
         sync += adr_l.r.eq(reset_a)
 
         # dest operand latch
-        sync += req_l.s.eq(self.go_ad_i|self.go_st_i)
+        sync += req_l.s.eq(self.go_ad_i|self.go_st_i|self.go_wr_i)
         sync += req_l.r.eq(reset_w)
 
         # store latch
-        sync += sto_l.s.eq(issue_i)#self.go_ad_i)
+        sync += sto_l.s.eq(self.go_rd_i) # XXX not sure which
         sync += sto_l.r.eq(reset_s)
 
         # outputs: busy and release signals
@@ -258,6 +259,10 @@ class LDSTCompUnit(Elaboratable):
             with m.If(self.req_rel_o):
                 m.d.comb += self.alu.n_ready_i.eq(1) # tells ALU "thanks got it"
 
+        # provide "done" signal: select req_rel for non-LD/ST, adr_rel for LD/ST
+        comb += self.done_o.eq((self.req_rel_o & ~op_ldst) |
+                               (self.adr_rel_o & op_ldst))
+
         # put the register directly onto the output bus on a go_write
         # this is "ALU mode".  go_wr_i *must* be deasserted on next clock
         with m.If(self.go_wr_i):
@@ -322,11 +327,11 @@ def wait_for(sig):
         if v:
             break
 
-def store(dut):
+def store(dut, src1, src2, imm):
     yield dut.oper_i.eq(LDST_OP_ST)
-    yield dut.src1_i.eq(4)
-    yield dut.src2_i.eq(9)
-    yield dut.imm_i.eq(2)
+    yield dut.src1_i.eq(src1)
+    yield dut.src2_i.eq(src2)
+    yield dut.imm_i.eq(imm)
     yield dut.issue_i.eq(1)
     yield
     yield dut.issue_i.eq(0)
@@ -342,11 +347,11 @@ def store(dut):
     yield
 
 
-def load(dut):
+def load(dut, src1, src2, imm):
     yield dut.oper_i.eq(LDST_OP_LD)
-    yield dut.src1_i.eq(4)
-    yield dut.src2_i.eq(9)
-    yield dut.imm_i.eq(2)
+    yield dut.src1_i.eq(src1)
+    yield dut.src2_i.eq(src2)
+    yield dut.imm_i.eq(imm)
     yield dut.issue_i.eq(1)
     yield
     yield dut.issue_i.eq(0)
@@ -357,16 +362,54 @@ def load(dut):
     yield from wait_for(dut.adr_rel_o)
     yield dut.go_ad_i.eq(1)
     yield from wait_for(dut.busy_o)
-    #wait_for(dut.stwd_mem_o)
+    yield
+    data = (yield dut.data_o)
     yield dut.go_ad_i.eq(0)
+    #wait_for(dut.stwd_mem_o)
+    return data
+
+
+def add(dut, src1, src2, imm, imm_mode = False):
+    yield dut.oper_i.eq(LDST_OP_ADDI if imm_mode else LDST_OP_ADD)
+    yield dut.src1_i.eq(src1)
+    yield dut.src2_i.eq(src2)
+    yield dut.imm_i.eq(imm)
+    yield dut.issue_i.eq(1)
+    yield
+    yield dut.issue_i.eq(0)
+    yield
+    yield dut.go_rd_i.eq(1)
+    yield from wait_for(dut.rd_rel_o)
+    yield dut.go_rd_i.eq(0)
+    yield from wait_for(dut.req_rel_o)
+    yield dut.go_wr_i.eq(1)
+    yield from wait_for(dut.busy_o)
+    yield
     data = (yield dut.data_o)
-    print ("read", data)
-    assert data != 0x0009
+    yield dut.go_wr_i.eq(0)
     yield
+    #wait_for(dut.stwd_mem_o)
+    return data
 
 def scoreboard_sim(dut):
-    yield from store(dut)
-    yield from load(dut)
+    # two STs (different addresses)
+    yield from store(dut, 4, 3, 2)
+    yield from store(dut, 2, 9, 2)
+    yield
+    # two LDs (deliberately LD from the 1st address then 2nd)
+    data = yield from load(dut, 4, 0, 2)
+    assert data == 0x0003
+    data = yield from load(dut, 2, 0, 2)
+    assert data == 0x0009
+    yield
+
+    # now do an add
+    data = yield from add(dut, 4, 3, 0xfeed)
+    assert data == 0x7
+
+    # and an add-immediate
+    data = yield from add(dut, 4, 0xdeef, 2, imm_mode=True)
+    assert data == 0x6
 
 
 class TestLDSTCompUnit(LDSTCompUnit):