# * bit 1: 0 = src1, 1 = IMM
# * bit 2: 1 = LD
# * bit 3: 1 = ST
+BIT0_ADD = 0
+BIT1_SRC = 1
+BIT2_ST = 2
+BIT3_LD = 3
+# convenience thingies.
LDST_OP_ADD = 0b0000 # plain ADD (src1 + src2) - use this ALU as an ADD
LDST_OP_SUB = 0b0001 # plain SUB (src1 - src2) - use this ALU as a SUB
LDST_OP_ADDI = 0b0010 # immed ADD (imm + src1)
LDST_OP_LD = 0b1010 # immed ADD plus ST op. ADD result is address
+
class LDSTCompUnit(Elaboratable):
""" LOAD / STORE / ADD / SUB Computation Unit
self.adr_rel_o = Signal(reset_less=True) # request address (from mem)
self.sto_rel_o = Signal(reset_less=True) # request store (to mem)
self.req_rel_o = Signal(reset_less=True) # request write (result)
+ self.done_o = Signal(reset_less=True) # final release signal
self.data_o = Signal(rwid, reset_less=True) # Dest out (LD or ALU)
self.addr_o = Signal(rwid, reset_less=True) # Address out (LD or ST)
reset_a = Signal(reset_less=True)
reset_s = Signal(reset_less=True)
reset_r = Signal(reset_less=True)
- comb += reset_b.eq(self.go_st_i | self.go_wr_i | self.go_die_i)
+ comb += reset_b.eq(self.go_st_i|self.go_wr_i|self.go_ad_i|self.go_die_i)
comb += reset_w.eq(self.go_wr_i | self.go_die_i)
comb += reset_s.eq(self.go_st_i | self.go_die_i)
comb += reset_r.eq(self.go_rd_i | self.go_die_i)
sync += adr_l.r.eq(reset_a)
# dest operand latch
- sync += req_l.s.eq(self.go_ad_i|self.go_st_i)
+ sync += req_l.s.eq(self.go_ad_i|self.go_st_i|self.go_wr_i)
sync += req_l.r.eq(reset_w)
# store latch
- sync += sto_l.s.eq(issue_i)#self.go_ad_i)
+ sync += sto_l.s.eq(self.go_rd_i) # XXX not sure which
sync += sto_l.r.eq(reset_s)
# outputs: busy and release signals
comb += src2_or_imm.eq(Mux(op_is_imm, self.imm_i, self.src2_i))
# create a latch/register for src1/src2 (include immediate select)
- latchregister(m, self.src1_i, self.alu.a, src_l.q)
- latchregister(m, self.src2_i, src2_r, src_l.q)
- latchregister(m, src2_or_imm, self.alu.b, src_sel)
+ latchregister(m, self.src1_i, self.alu.a, src_l.q, name="src1_r")
+ latchregister(m, self.src2_i, src2_r, src_l.q, name="src2_r")
+ latchregister(m, src2_or_imm, self.alu.b, src_sel, name="imm_r")
# create a latch/register for the operand
oper_r = Signal(self.opwid, reset_less=True) # Dest register
- latchregister(m, self.oper_i, oper_r, self.issue_i)
+ latchregister(m, self.oper_i, oper_r, self.issue_i, name="operi_r")
alu_op = Cat(op_alu, 0, op_is_imm) # using alu_hier, here.
comb += self.alu.op.eq(alu_op)
# and one for the output from the ALU
data_r = Signal(self.rwid, reset_less=True) # Dest register
- latchregister(m, self.alu.o, data_r, alulatch)
+ latchregister(m, self.alu.o, data_r, alulatch, "aluo_r")
# decode bits of operand (latched)
- comb += op_alu.eq(oper_r[0])
- comb += op_is_imm.eq(oper_r[1])
- comb += op_is_ld.eq(oper_r[2])
- comb += op_is_st.eq(oper_r[3])
+ comb += op_alu.eq(oper_r[BIT0_ADD]) # ADD/SUB
+ comb += op_is_imm.eq(oper_r[BIT1_SRC]) # IMMED/reg
+ comb += op_is_st.eq(oper_r[BIT2_ST]) # OP is ST
+ comb += op_is_ld.eq(oper_r[BIT3_LD]) # OP is LD
comb += op_ldst.eq(op_is_ld | op_is_st)
comb += self.load_mem_o.eq(op_is_ld & self.go_ad_i)
comb += self.stwd_mem_o.eq(op_is_st & self.go_st_i)
with m.If(self.req_rel_o):
m.d.comb += self.alu.n_ready_i.eq(1) # tells ALU "thanks got it"
+ # provide "done" signal: select req_rel for non-LD/ST, adr_rel for LD/ST
+ comb += self.done_o.eq((self.req_rel_o & ~op_ldst) |
+ (self.adr_rel_o & op_ldst))
+
# put the register directly onto the output bus on a go_write
# this is "ALU mode". go_wr_i *must* be deasserted on next clock
with m.If(self.go_wr_i):
if v:
break
-def store(dut):
- yield dut.oper_i.eq(LDST_OP_LD)
- yield dut.src1_i.eq(4)
- yield dut.src2_i.eq(9)
- yield dut.imm_i.eq(2)
+def store(dut, src1, src2, imm):
+ yield dut.oper_i.eq(LDST_OP_ST)
+ yield dut.src1_i.eq(src1)
+ yield dut.src2_i.eq(src2)
+ yield dut.imm_i.eq(imm)
yield dut.issue_i.eq(1)
yield
yield dut.issue_i.eq(0)
yield from wait_for(dut.adr_rel_o)
yield dut.go_st_i.eq(1)
yield from wait_for(dut.sto_rel_o)
- #wait_for(dut.stwd_mem_o)
+ wait_for(dut.stwd_mem_o)
yield dut.go_st_i.eq(0)
+ yield
-def load(dut):
+def load(dut, src1, src2, imm):
yield dut.oper_i.eq(LDST_OP_LD)
- yield dut.src1_i.eq(4)
- yield dut.src2_i.eq(9)
- yield dut.imm_i.eq(2)
+ yield dut.src1_i.eq(src1)
+ yield dut.src2_i.eq(src2)
+ yield dut.imm_i.eq(imm)
yield dut.issue_i.eq(1)
yield
yield dut.issue_i.eq(0)
yield from wait_for(dut.rd_rel_o)
yield dut.go_rd_i.eq(0)
yield from wait_for(dut.adr_rel_o)
- #yield dut.go_ad_i.eq(1)
- #yield
- #yield dut.go_ad_i.eq(0)
- yield dut.go_st_i.eq(1)
+ yield dut.go_ad_i.eq(1)
yield from wait_for(dut.busy_o)
+ yield
+ data = (yield dut.data_o)
+ yield dut.go_ad_i.eq(0)
#wait_for(dut.stwd_mem_o)
- yield dut.go_st_i.eq(0)
+ return data
+
+
+def add(dut, src1, src2, imm, imm_mode = False):
+ yield dut.oper_i.eq(LDST_OP_ADDI if imm_mode else LDST_OP_ADD)
+ yield dut.src1_i.eq(src1)
+ yield dut.src2_i.eq(src2)
+ yield dut.imm_i.eq(imm)
+ yield dut.issue_i.eq(1)
+ yield
+ yield dut.issue_i.eq(0)
+ yield
+ yield dut.go_rd_i.eq(1)
+ yield from wait_for(dut.rd_rel_o)
+ yield dut.go_rd_i.eq(0)
+ yield from wait_for(dut.req_rel_o)
+ yield dut.go_wr_i.eq(1)
+ yield from wait_for(dut.busy_o)
+ yield
+ data = (yield dut.data_o)
+ yield dut.go_wr_i.eq(0)
+ yield
+ #wait_for(dut.stwd_mem_o)
+ return data
def scoreboard_sim(dut):
- yield from store(dut)
+ # two STs (different addresses)
+ yield from store(dut, 4, 3, 2)
+ yield from store(dut, 2, 9, 2)
+ yield
+ # two LDs (deliberately LD from the 1st address then 2nd)
+ data = yield from load(dut, 4, 0, 2)
+ assert data == 0x0003
+ data = yield from load(dut, 2, 0, 2)
+ assert data == 0x0009
+ yield
+
+ # now do an add
+ data = yield from add(dut, 4, 3, 0xfeed)
+ assert data == 0x7
+
+ # and an add-immediate
+ data = yield from add(dut, 4, 0xdeef, 2, imm_mode=True)
+ assert data == 0x6
class TestLDSTCompUnit(LDSTCompUnit):
projects / soc.git / blobdiff