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[soc.git] / src / soc / experiment / compldst.py

diff --git a/src/soc/experiment/compldst.py b/src/soc/experiment/compldst.py
index ea9827a04b484d54958b50f54e43641ce0ecc330..206f44876b00b6c1d94716e624a03e81208120d4 100644 (file)
--- a/src/soc/experiment/compldst.py
+++ b/src/soc/experiment/compldst.py
@@ -117,6 +117,7 @@ class LDSTCompUnit(Elaboratable):
         self.adr_rel_o = Signal(reset_less=True) # request address (from mem)
         self.sto_rel_o = Signal(reset_less=True) # request store (to mem)
         self.req_rel_o = Signal(reset_less=True) # request write (result)
+        self.done_o = Signal(reset_less=True) # final release signal
         self.data_o = Signal(rwid, reset_less=True) # Dest out (LD or ALU)
         self.addr_o = Signal(rwid, reset_less=True) # Address out (LD or ST)
 
@@ -191,7 +192,7 @@ class LDSTCompUnit(Elaboratable):
         sync += req_l.r.eq(reset_w)
 
         # store latch
-        sync += sto_l.s.eq(issue_i)# XXX hmmm... |self.go_st_i)
+        sync += sto_l.s.eq(self.go_rd_i) # XXX not sure which
         sync += sto_l.r.eq(reset_s)
 
         # outputs: busy and release signals
@@ -258,6 +259,10 @@ class LDSTCompUnit(Elaboratable):
             with m.If(self.req_rel_o):
                 m.d.comb += self.alu.n_ready_i.eq(1) # tells ALU "thanks got it"
 
+        # provide "done" signal: select req_rel for non-LD/ST, adr_rel for LD/ST
+        comb += self.done_o.eq((self.req_rel_o & ~op_ldst) |
+                               (self.adr_rel_o & op_ldst))
+
         # put the register directly onto the output bus on a go_write
         # this is "ALU mode".  go_wr_i *must* be deasserted on next clock
         with m.If(self.go_wr_i):