change CSV LD/ST update field to LDSTMode (support cix)

[soc.git] / src / soc / experiment / compldst_multi.py

diff --git a/src/soc/experiment/compldst_multi.py b/src/soc/experiment/compldst_multi.py
index c1f4f4372f0a5ce075ad05bc195ca00e90a0fb62..2bc009378ec7d350c94149a6e53d4b0e86dbcfcb 100644 (file)
--- a/src/soc/experiment/compldst_multi.py
+++ b/src/soc/experiment/compldst_multi.py
@@ -90,7 +90,7 @@ from soc.experiment.compalu_multi import go_record, CompUnitRecord
 from soc.experiment.l0_cache import PortInterface
 from soc.fu.regspec import RegSpecAPI
 
-from soc.decoder.power_enums import InternalOp, Function
+from soc.decoder.power_enums import InternalOp, Function, LDSTMode
 from soc.fu.ldst.ldst_input_record import CompLDSTOpSubset
 from soc.decoder.power_decoder2 import Data
 
@@ -390,7 +390,8 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable):
         # decode bits of operand (latched)
         comb += op_is_st.eq(oper_r.insn_type == InternalOp.OP_STORE) # ST
         comb += op_is_ld.eq(oper_r.insn_type == InternalOp.OP_LOAD)  # LD
-        op_is_update = oper_r.update                                 # UPDATE
+        op_is_update = oper_r.ldst_mode == LDSTMode.update           # UPDATE
+        op_is_cix = oper_r.ldst_mode == LDSTMode.cix           # cache-inhibit
         comb += self.load_mem_o.eq(op_is_ld & self.go_ad_i)
         comb += self.stwd_mem_o.eq(op_is_st & self.go_st_i)
         comb += self.ld_o.eq(op_is_ld)