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[soc.git] / src / soc / experiment / dcache.py

diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index bbb655f01632d39b72f1eddd09d4c7ddf2bede89..4cd1c0abdac53e920a011eb02c866b13c4d95c5c 100644 (file)
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -573,7 +573,7 @@ class DTLBUpdate(Elaboratable):
         # on a one-clock delay, hence the register
         r_tlb_way        = TLBRecord("r_tlb_way")
         with m.If(r_delay):
-            # on one clock delay, output the contents of the read port(s)
+            # on one clock delay, capture the contents of the read port(s)
             comb += self.tlb_way.tag.eq(rd_tagway.data)
             comb += self.tlb_way.pte.eq(rd_pteway.data)
             sync += r_tlb_way.tag.eq(rd_tagway.data)