rename PLRU modules to avoid conflict in microwatt

[soc.git] / src / soc / experiment / icache.py

diff --git a/src/soc/experiment/icache.py b/src/soc/experiment/icache.py
index 02b54a03932f56d151b6c553950b3d4385341d15..e9c8ed1b1db45b50e6eb7d6158706aaeee6ed14e 100644 (file)
--- a/src/soc/experiment/icache.py
+++ b/src/soc/experiment/icache.py
@@ -419,7 +419,8 @@ class ICache(FetchUnitInterface, Elaboratable, ICacheConfig):
             return
 
 
-        m.submodules.plrus = plru = PLRUs(self.NUM_LINES, self.WAY_BITS)
+        m.submodules.plrus = plru = PLRUs("itag", self.NUM_LINES,
+                                                  self.WAY_BITS)
         comb += plru.way.eq(r.hit_way)
         comb += plru.valid.eq(r.hit_valid)
         comb += plru.index.eq(self.get_index(r.hit_nia))
@@ -704,7 +705,7 @@ class ICache(FetchUnitInterface, Elaboratable, ICacheConfig):
         # If we are still sending requests, was one accepted?
         with m.If(~bus.stall & r.wb.stb):
             # That was the last word? We are done sending.  Clear stb
-            with m.If(self.is_last_row_addr(r.wb.adr, r.end_row_ix)):
+            with m.If(self.is_last_row_addr(r.req_adr, r.end_row_ix)):
                 sync += Display("IS_LAST_ROW_ADDR r.wb.addr:%x "
                          "r.end_row_ix:%x r.wb.stb:%x",
                          r.wb.adr, r.end_row_ix, r.wb.stb)