connect up WB SRAM to dcache test

[soc.git] / src / soc / experiment / mem_types.py

diff --git a/src/soc/experiment/mem_types.py b/src/soc/experiment/mem_types.py
index 829d68186afbb87bd14a99fea2d2d38f50a6a0ef..20714a51ec4773f83a64c9ce998ef8aad7f95d75 100644 (file)
--- a/src/soc/experiment/mem_types.py
+++ b/src/soc/experiment/mem_types.py
@@ -18,8 +18,8 @@ class DCacheToLoadStore1Type(RecordObject):
 
 
 class DCacheToMMUType(RecordObject):
-    def __init__(self):
-        super().__init__()
+    def __init__(self, name=None):
+        super().__init__(name=name)
         self.stall         = Signal()
         self.done          = Signal()
         self.err           = Signal()
@@ -86,8 +86,8 @@ class MMUToLoadStore1Type(RecordObject):
         self.sprval        = Signal(64)
 
 class MMUToDCacheType(RecordObject):
-    def __init__(self):
-        super().__init__()
+    def __init__(self, name=None):
+        super().__init__(name=name)
         self.valid         = Signal()
         self.tlbie         = Signal()
         self.doall         = Signal()