more code-comments

[soc.git] / src / soc / experiment / mmu.py

diff --git a/src/soc/experiment/mmu.py b/src/soc/experiment/mmu.py
index adef05ffb8535c37adca1478a121a36f22edc388..f139e85aa3b9fa8c60ae20e07cc5e840471f9d28 100644 (file)
--- a/src/soc/experiment/mmu.py
+++ b/src/soc/experiment/mmu.py
@@ -539,12 +539,14 @@ class MMU(Elaboratable):
                 sync += Display("   RADIX_FINISH")
                 comb += v.state.eq(State.IDLE)
 
+        # check and report either error or done.
         with m.If((v.state == State.RADIX_FINISH) |
                  ((v.state == State.RADIX_LOAD_TLB) & r.iside)):
             comb += v.err.eq(v.invalid | v.badtree | v.segerror
                              | v.perm_err | v.rc_error)
             comb += v.done.eq(~v.err)
 
+        # PID is only valid if MSB of address is zero
         with m.If(~r.addr[63]):
             comb += effpid.eq(r.pid)