Merge branch 'master' of ssh://git.libre-riscv.org:922/soc

[soc.git] / src / soc / experiment / pimem.py

diff --git a/src/soc/experiment/pimem.py b/src/soc/experiment/pimem.py
index b84b3040da3be6b250e52c554e94c022831ece3b..b9c05df5567378f736a9872511f751e39d2a6017 100644 (file)
--- a/src/soc/experiment/pimem.py
+++ b/src/soc/experiment/pimem.py
@@ -226,6 +226,7 @@ class PortInterfaceBase(Elaboratable):
         pr = ~pi.priv_mode
         dr = pi.virt_mode   # not yet used
         sf = pi.mode_32bit   # not yet used
+        msr = MSRSpec(pr=pr, dr=dr, sf=sf)
 
         # detect busy "edge"
         busy_delay = Signal()